Haruki Yokoyama

Fundamental oscillation of resonant tunneling diodes above 1 THz at room temperature

Fundamental oscillations up to 1.04 THz were achieved in resonant tunneling diodes at room temperature. A graded emitter and thin barriers were introduced in GaInAs/AlAs double-barrier resonant tunneling diodes for reductions of the transit time in the collector depletion region and the resonant tunneling time, respectively. Output powers were 7 μW at 1.04 THz and around 10 μW in 0.9–1 THz region. A change in oscillation frequency of about 4% with bias voltage was also obtained.

ULTRAHIGH-SPEED INTEGRATED CIRCUITS USING INP-BASED HEMTS

The device technologies for 0.1-µm-gate InP-based high electron mobility transistors (HEMTs), which consist of an InAlAs/InGaAs modulation-doped structure on an InP substrate, are described. They yielded a current gain cutoff frequency (fT) of over 180 GHz and a transconductance (gm) of over 1 S/mm in circuits. An InP recess-etch stopper improved the uniformity of threshold voltage and enabled us to apply HEMTs in digital ICs. A diode consisting of an InAlAs Schottky junction is monolithically integrated with a HEMT and used as a level shifter in digital ICs. By combining novel circuit technologies and the HEMT-IC technologies, the maximum operation speed of IC has been pushed up to over 40 Gbit/s. As a benchmark for future large-capacity networks, electrically multiplexed and demultiplexed 40 Gbit/s, 300 km transmission was successfully demonstrated using the device technologies described here.

Formation of Cubic Boron Nitride Film on Si with Boron Buffer Layers

The c-BN (cubic BN)/BNX/B/Si structure was formed using plasma CVD techniques. In contrast with the direct growth of c-BN films, the adherence of the structure on Si was entirely satisfactory. The characterization of buffer layers (BN(X=0.6), BN(X=0.3), B) by X-ray photoelectron, infrared absorption spectroscopies and internal stress measurements show that the c-BN/BNX/B/Si structure is useful as a mechanically stable passivation film.

30-nm two-step recess gate InP-Based InAlAs/InGaAs HEMTs

Two-step recess gate technology has been developed for sub-100-nm gate InP-based InAlAs/InGaAs high-electron mobility transistors (HEMTs). This gate structure is found to be advantageous for the preciseness of the metallurgical gate length as well as a comparable stability to the conventional gate structure with an InP etch stop layer. The two-step recess gate is optimized focusing on the lateral width of the gate recess. Due to the stability of the gate recess with an InP surface, a laterally wide gate recess gives the maximum cutoff frequency, lower gate leakage current, smaller output conductance and higher maximum frequency of oscillation. Finally, the uniformity of the device characteristics evaluated for sub-100-nm HEMTs with the optimized recess width. The result reveals the significant role of the short channel effects on the device uniformity.

High-performance 0.1-/spl mu/m gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology

Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMTs (E-HEMTs) is described for the first time. Most important issue for the fabrication of E-HEMTs is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 /spl Omega//spl middot/mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-/spl mu/m gate E-HEMTs. This is therefore one of the promising devices for ultra-high-speed applications.

Improved Recessed-Gate Structure for Sub-0.1-µm-Gate InP-Based High Electron Mobility Transistors

An improved recessed-gate structure for high-performance short-gate InP-based InAlAs/InGaAs high electron mobility transistors (HEMTs) is presented. The effective gate length of the HEMTs is found to be related to the electron density in the side-etched region between the gate and the ohmic capped region. The higher electron density in the side-etched region is efficiently suppresses the effective gate length. A new gate recess process, which consists of a sequence of wet-chemical etching and Ar-plasma etching, enables us to reduce the effective gate length. The new recessed-gate structure successfully provides improved performance with high uniformity. A cutoff frequency of 300 GHz is achieved even with 0.07-µm-gate HEMTs.

Function of Substrate Bias Potential for Formation of Cubic Boron Nitride Films in Plasma CVD Technique

Cubic BN thin films are formed in RF discharge in B2H6 and N2 at low pressures under a magnetic field to confine the plasma, for negatively self-biased substrate electrodes. Ion bombardment on the growing surface is suggested to play an important role in the formation of cubic BN. The deposited films are characterized by infrared absorption spectroscopy and transmission electron microscopy which show that they are composed of microcrystals of cubic BN with 100-200 A grain size.

Fundamental Oscillation of up to 831 GHz in GaInAs/AlAs Resonant Tunneling Diode

A fundamental oscillation of up to 831 GHz was observed at room temperature in GaInAs/AlAs resonant tunneling diodes integrated with planar slot antennas. The thickness of the collector spacer layer was optimized (20 nm) and the mesa area (≪1 µm²) was reduced in order to reduce the resonant tunneling diode capacitance. Reduction in the negative differential conductance in the small mesa area was prevented by increasing the emitter doping concentration (3 × 10¹⁸ cm⁻³) which resulted in an ultra-high peak current density (18 mA/µm²) with a peak-to-valley current ratio of 2. The dependence of oscillation frequency on the mesa area was also studied. The output power was at least 1 µW.

Systematic study of insulator deposition effect (Si3N4, SiO2, AlN, and Al2O3) on electrical properties in AlGaN/GaN heterostructures

To systematically examine the effect of insulator deposition on the electrical properties in AlGaN/GaN heterostructures, the Si- and Al-based insulators (Si3N4, SiO2, AlN, and Al2O3) have been deposited on Al0.3Ga0.7N/GaN heterostructures. A significant increase in two-dimensional electron gas (2DEG) density (Ns) was observed for all the insulators with the order of Ns(Al2O3) > Ns(AlN) ~ Ns(SiO2) > Ns(Si3N4) > N0 (N0: Ns without insulators). This resulted in a decrease in sheet resistance (R) with the smallest order of R(Al2O3) < R(AlN) < R(Si3N4) < R0 ~ R(SiO2) (R0: R without insulators). This order is the same as that of Ns except for SiO2, where the 2DEG mobility largely degraded due to the diffusion of Si atoms into nitride layers. The increase in Ns was theoretically analyzed in terms of the change in the potential profile, and the following parameters were extracted: (i) the surface potential barrier (B), and (ii) the interface charge (NInt) between an insulator and AlGaN. B (eV) was estimated to be 1.7 (Si3N4), 2.2 (AlN), 2.7 (Al2O3), and 3.6 (SiO2), exhibiting a positive correlation between B and the bandgap of the insulator. NInt (1013 cm-2) was estimated to be ~0 (Si3N4), 0.1 (SiO2), 0.3 (AlN), and 0.5 (Al2O3); thus, the interface was found to be positively charged for AlN and Al2O3, whereas it was found to be almost neutral for Si3N4 and SiO2. Thus, the insulator deposition effect has been shown to be significant and to vary among insulators. The analysis shown here offers a guideline for understanding and designing the electrical properties in AlGaN/GaN heterostructures, where insulators are deposited as surface passivation and/or gate insulators.

30-nm-Gate InP-Based Lattice-Matched High Electron Mobility Transistors with 350 GHz Cutoff Frequency

The device characteristics and fabrication of 30-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates are reported. The gate length of 30 nm is achieved for a T-shaped gate geometry, which is necessary to minimize gate resistance for short-gate HEMTs, by using fullerene-incorporated nanocomposite resist in the electron beam direct writing of the bottom of the gate. In addition, the two-step-recess gate technology is used to minimize the extension of effective gate length. The devices provide excellent RF characteristics; a record cutoff frequency of 350 GHz is achieved.