Takatomo Enoki

High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies

High performance InP-based InAlAs/InGaAs enhancement-mode HEMTs are demonstrated using two improved approaches to device structure design and fabrication, i.e., nonalloyed ohmic contacts and Pt-based buried-gate technologies, to reduce the source resistance (R/sub S/). With specially designed cap layer structures, nonalloyed ohmic contacts to the device channel were obtained providing contact resistance as low as 0.067 /spl Omega//spl middot/mm. Furthermore, in device fabrication, a Pt-based buried-gate approach is used in which depletion-mode HEMTs are first intentionally fabricated, and then, the Pt-based gate metal is annealed at 250/spl deg/C, causing the Pt-InAlAs reaction to take place under the gate electrode so that Pt sinks into InAlAs and depletes the channel. As a result, the depletion-mode HEMTs are changed to enhancement-mode, while the channel region between the source and gate electrodes remain undepleted, and therefore, the small R/sub S/ of 0.2 /spl Omega//spl middot/mm can be maintained. Excellent maximum transconductance of 1170 mS/mm was obtained for a 0.5-/spl mu/m-gate device. A maximum current-gain cutoff frequency f/sub T/ of 41.2 GHz and maximum unilateral power-gain cutoff frequency f/sub max/ of 61 GHz were demonstrated for a 0.6-/spl mu/m-gate enhancement-mode HEMT.

0.05-μm-Gate InAlAs/InGaAs High Electron Mobility Transistor and Reduction of Its Short-Channel Effects

In this paper, we discusse the advantages of thinning the channel on short-channel effects for lattice-matched InAlAs/InGaAs high electron mobility transistors (HEMTs) with sub-0.1-µm-long gates with regard to the performance of a 0.05-µm-gate device. To fabricate a sub-0.1-µm gate, the opening shape of the gate-footprint is controlled by using a bilayer dielectric film system and RIE side etching. The device shows a current gain cutoff frequency of 300 GHz and g m/g d ratio of 15. Thinning the channel and the barrier down to 100 A improves carrier confinement and subthreshold characteristics and is indispensable for reducing the short-channel effects in the sub-0.1-µm-gate-length region.

Improved InAlAs/InGaAs HEMT characteristics by inserting an InAs layer into the InGaAs channel

An InAlAs/InGaAs HEMT with a thin InAs layer inserted into the InGaAs channel is proposed and its electron transport properties and device performances have been investigated. By optimizing the thickness and the exact point of insertion in the InAs layer, the mobility and electron velocity at 300 K have been increased by 30% and 15%, respectively, compared to the conventional heterostructure. In addition, a maximum intrinsic transconductance of 970 mS/mm and a maximum current gain cutoff frequency of 58.1 GHz have been attained by a 0.6 mu m-gate-length device.<<ETX>>

An analysis of the kink phenomena in InAlAs/InGaAs HEMT's using two-dimensional device simulation

Kink phenomena in InAlAs/InGaAs HEMTs are investigated using a two-dimensional (2-D) device simulation that takes into account impact ionization, including nonlocal field effects, and the surface states in a side-etched region at the gate periphery. The simulation model enables us to represent the kink, and it is found that the accumulation of holes generated by the impact ionization has the channel electron density in the side-etched region increase at the bias point where kink appears. When the electron density in the side-etched region is small, the hole accumulation causes a significant increase in that electron density, resulting in a large kink. The simulation results suggest a model in which the kink is described in terms of the modification of the parasitic source resistance induced by the hole accumulation. This model implies a way to eliminate the kink, that is, keeping the electron density in the side-etched region high.

ULTRAHIGH-SPEED INTEGRATED CIRCUITS USING INP-BASED HEMTS

The device technologies for 0.1-µm-gate InP-based high electron mobility transistors (HEMTs), which consist of an InAlAs/InGaAs modulation-doped structure on an InP substrate, are described. They yielded a current gain cutoff frequency (fT) of over 180 GHz and a transconductance (gm) of over 1 S/mm in circuits. An InP recess-etch stopper improved the uniformity of threshold voltage and enabled us to apply HEMTs in digital ICs. A diode consisting of an InAlAs Schottky junction is monolithically integrated with a HEMT and used as a level shifter in digital ICs. By combining novel circuit technologies and the HEMT-IC technologies, the maximum operation speed of IC has been pushed up to over 40 Gbit/s. As a benchmark for future large-capacity networks, electrically multiplexed and demultiplexed 40 Gbit/s, 300 km transmission was successfully demonstrated using the device technologies described here.

Design and characteristics of InGaAs/InP composite-channel HFET's

A design for composite-channel structures consisting of an InGaAs channel and an InP subchannel for use as heterostructure field-effect transistors is presented for the first time. This novel channel structure takes advantage of both the high drift velocity and low impact ionization of InP at high electric fields as well as the high electron mobility of InGaAs at low electric fields. It is shown that the doping density of the InP subchannel is the key parameter to realize the advantages of the composite channel. A very high transconductance of 1.29 S/mm and a current gain cutoff frequency of 68.7 GHz are achieved with 0.6 and 0.7 /spl mu/m gates, respectively. The average velocity of electrons in the composite channel is 2.9/spl times/10/sup 7/ cm/s. The devices have no kink phenomena in their I-V characteristics possibly due to low impact ionization in the InP subchannel. >

An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs

We report on an 80-Gbit/s 2:1 selector-type multiplexer IC using InAlAs/InGaAs/InP HEMTs incorporating a high-speed double layer interconnection process with a low permittivity insulator. The record operating data rate was measured on a 3-inch wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time.

Loss-compensated distributed baseband amplifier IC's for optical transmission systems

We describe a distributed baseband amplifier using a new loss compensation technique for the drain artificial line. The new loss compensation circuit improves a high-frequency performance of the amplifier and makes the gain bandwidth product of the amplifier larger than that of conventional ones. We also use dc matching terminations and dumping resistors for the gate and drain artificial lines to obtain flat gain from frequencies as low as 0 Hz. One IC fabricated using 0.1 /spl mu/m-gatelength InAlAs/InGaAs/InP HEMTs has a gain of 16 dB over a 0-to-50 GHz band, resulting in a gain bandwidth product of about 300 GHz. Another IC has a gain of 10 dB over a 0-to-90 GHz band. These are the highest gain bandwidth product and the widest band reported for baseband amplifier ICs applicable to optical transmission systems.

30-nm two-step recess gate InP-Based InAlAs/InGaAs HEMTs

Two-step recess gate technology has been developed for sub-100-nm gate InP-based InAlAs/InGaAs high-electron mobility transistors (HEMTs). This gate structure is found to be advantageous for the preciseness of the metallurgical gate length as well as a comparable stability to the conventional gate structure with an InP etch stop layer. The two-step recess gate is optimized focusing on the lateral width of the gate recess. Due to the stability of the gate recess with an InP surface, a laterally wide gate recess gives the maximum cutoff frequency, lower gate leakage current, smaller output conductance and higher maximum frequency of oscillation. Finally, the uniformity of the device characteristics evaluated for sub-100-nm HEMTs with the optimized recess width. The result reveals the significant role of the short channel effects on the device uniformity.

Improved Recessed-Gate Structure for Sub-0.1-µm-Gate InP-Based High Electron Mobility Transistors

An improved recessed-gate structure for high-performance short-gate InP-based InAlAs/InGaAs high electron mobility transistors (HEMTs) is presented. The effective gate length of the HEMTs is found to be related to the electron density in the side-etched region between the gate and the ohmic capped region. The higher electron density in the side-etched region is efficiently suppresses the effective gate length. A new gate recess process, which consists of a sequence of wet-chemical etching and Ar-plasma etching, enables us to reduce the effective gate length. The new recessed-gate structure successfully provides improved performance with high uniformity. A cutoff frequency of 300 GHz is achieved even with 0.07-µm-gate HEMTs.