Haruo Shimamoto
Mitsubishi
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Publication
Featured researches published by Haruo Shimamoto.
electronic components and technology conference | 2002
Yasumi Uegai; Akinobu Kawazu; Qiang Wu; Hironori Matsushima; Masatoshi Yasunaga; Haruo Shimamoto
Evaluation of the thermal fatigue life of the solder joints that connect the BGA package to the system board electrically and mechanically, and the improvement of precision are important issues in the development of BGA/FBGA packages. The fatigue life of the BGA solder joint consists of a process of micro-crack initiation followed by its propagation. This results in the increase of electrical resistance and the lifetime of solder joint. It is necessary to develop an evaluation method using crack growth - which defines most of the total life - for more accurate prediction of the lifetime of BGA/FBGA solder joints. The fatigue crack growth rate of BGA solder joints was measured by using actual BGA solder joint specimens in order to evaluate the thermal cycle life of BGA packages. Eutectic solder was used for the solder joint material. Isothermal mechanical fatigue tests were performed on these specimens and thermal cycle tests were performed under the temperature condition of 0/spl lrarr2/+100/spl deg/C. The crack propagation length was measured by observing the fracture surface of the solder joint before the joint was broken interrupting the fatigue test. The fatigue crack growth rate was then evaluated. A structural analysis using FEM was made to determine the equivalent plastic strain and the plastic strain energy density of BGA solder joints in consideration of the nonlinear stress-strain relation of the solder material. The fatigue crack growth curve of BGA solder joints was evaluated combining the above experimental and analytical results.
electronic components and technology conference | 2017
Naoya Watanabe; Hidekazu Kikuchi; Azusa Yanagisawa; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi; Akio Nakamura
To confirm the effectiveness of the via-last through silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer, we evaluated the metal contamination caused by this process. The metal contamination generated near the TSV was investigated by measuring the reverse-bias leakage current of n+/p diodes placed near the TSV. The TSV diameter was 6 µm and the n+/p diode size was 0.6 × 2 µm. The distance between the n+/p diodes and the TSV was 1-10 µm. The notching size was controlled by the etching time. The reverse bias leakage current was small regardless of the distance between the TSV and n+/p diode when the notching size was small (
Archive | 2003
Tetsuya Ueda; Osami Nakagawa; Haruo Shimamoto; Yasuhiro Teraoka; Seiji Takemura
Archive | 1994
Akiyoshi Sawai; Haruo Shimamoto; Toru Tachikawa; Jun Shibata
Archive | 1997
Akiyoshi Sawai; Haruo Shimamoto; Toru Tachikawa; Jun Shibata
Archive | 1991
Tetsuya Ueda; Haruo Shimamoto; Yasuhiro Teraoka; Hideya Yagoura; Hiroshi Seki
Archive | 1995
Kazushi Hatauchi; Haruo Shimamoto
Archive | 1988
Yasuhiro Teraoka; Tetsuya Ueda; Hideya Yagoura; Haruo Shimamoto; Shigeyuki Nango; Toshinobu Banjo; Hiroshi Seki
Archive | 1992
Haruo Shimamoto; Jun Shibata; Toru Tachikawa; Tetsuya Ueda; Hiroshi Seki
Archive | 1988
Tetsuya Ueda; Haruo Shimamoto; Hideya Yagoura; Hiroshi Seki; Yasuhiro Teraoka
Collaboration
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National Institute of Advanced Industrial Science and Technology
View shared research outputsNational Institute of Advanced Industrial Science and Technology
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