Haruyuki Tago

Vector unit architecture for emotion synthesis

Two vector units embedded in the emotion engine chip support high-quality 3D graphics, emotion synthesis, and 300-MHz, 5.5-GFLOPS operation for the recently introduced PlayStation2 game entertainment system.

30-ns 55-b shared radix 2 division and square root using a self-timed circuit

A shared radix 2 division and square root implementation using a self-timed circuit is presented. The same execution time for division and square root is achieved by using an on-the-fly digit decoding and a root multiple generation technique. Most of the hardware is shared, and only several multiplexers are required to exchange a divisor multiple and a root multiple. Moreover, quotient selection logic is accelerated by a new algorithm using a 3-b carry propagation adder. The implementation of the shared division and square root unit is realized by assuming 0.3 /spl mu/m CMOS technology. The wiring capacitance and other parasitic parameters are taken into account. The execution time of floating point 55-b full mantissa division and square root is expected to be less than 30 ns in the worst case of an input vector determined by an intensive circuit simulation.<<ETX>>

A real-time software platform for the Cell processor

Scalability, efficiency, and programmability are essential for using the cell processor in consumer electronics. A real-time resource scheduler virtualizes the processor cores and ensures the application of real-time constraints at the system level. These features let the platform control resource usage and help exploit the power management features implemented in the cell processor.

A 500 MHz 1-stage 32 bit ALU with self-running test circuit

A 500 MHz 1-stage 32 bit ALU has been designed and fabricated using 0.3 /spl mu/m CMOS process. Main features are a 1.56 ns DPL (Double path-transistor logic) adder and a compact barrel shifter using a newly developed 4-input MUX scheme. A BIST (built-in self test) circuit enables 500 MHz real-time testing. The chip size is 1 mm/spl times/0.38 mm.

High performance I/O processors for real-time pulse handling

Two peripheral processor LSIs, the FTI (fast timed input port) and the FTO (fast timed output port), have been developed for real-time pulse handling. By using the time-wheel scheme, these processors provide a high-level command interface with the host CPU, thus alleviating the CPU load. New features, such as time difference measurement between channels and user reprogrammability during operation have been realized using this approach. The prototypes of both FTI and FTO were designed and fabricated using a 1.5- mu m CMOS sea-of-gates technology, and demonstrated the effectiveness of the time-wheel scheme.<<ETX>>