Hasan Sharifi

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA∕mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3–5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ∼3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2∕Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge’s constant measured by low frequency noise spectral density characterization is 3.7×10−5 for the same device.

Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives

This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 mum are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-mum CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved

Characterization of Parylene-N as Flexible Substrate and Passivation Layer for Microwave and Millimeter-Wave Integrated Circuits

Investigation of Parylene-N (Pa-N) as a flexible substrate, multilayer dielectric material, and passivation layer for microwave and millimeter-wave integrated circuits is presented. For the first time, the electrical properties of Parylene-N have been characterized up to 60 GHz using various microstrip ring resonators and transmission lines. As a flexible substrate, Parylene-N measures a nearly invariant relative dielectric constant (epsivr) of 2.35-2.4, and a loss tangent (tan delta) of lower than 0.0006 for frequencies up to 60 GHz. Because of the above properties, as a passivation layer, Parylene-N causes insignificant modifications to the properties of underlying passive and active structures. Measurement of coplanar waveguide transmission lines before and after passivation reveals that a 5-mum Parylene-N barely changes the insertion loss (below measurement accuracy) while a 10-mum-thick Parylene-N layer increases the insertion loss by only 0.007 dB/mm (below measurement error) at 40 GHz. Ring resonators before and after a 5 or 10 mum passivation show a frequency shift of less than 0.05% or 1.51%, respectively, up to 40 GHz. The influence of Parylene-N passivation on the RF performance of GaAs MESFETs is also found to be negligible. Finally, humidity studies with dew point sensors reveal that with a 10- mum-thick passivation at 25degC and 100% relative humidity, the MTTF is about 481.6 days. In summary, the results indicate that Parylene-N is an excellent and promising material for application at microwave and millimeter-wave frequencies.

3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

Parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15-¿ m-thick parylene-N layer and 0.56 dB/mm for a 50-¿ CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with under passes that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13-¿m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of +4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.

Low-Loss Coplanar Waveguide Transmission Lines and Vertical Interconnects on Multi-Layer Parylene-N

Coplanar waveguide transmission lines and vertical interconnects are implemented on a thick (15µm) Parylene-N dielectric layer over a lossy CMOS-grade Si substrate. Devices are measured up to 40GHz and show very low loss behavior. Low loss tangent and low dielectric constant characteristics of Parylene-N result in significant improvement of transmission lines and interconnects compared to those implemented in a standard Si integrated circuit technology.

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.

Heterogeneously Integrated 10Gb/s CMOS Optoelectronic Receiver for Long Haul Telecommunication

A fully integrated 10 Gb/s 1.3 to 1.55 mum CMOS optoelectronic receiver is demonstrated for the first time. By heterogeneously integrating of a CMOS transimpedance amplifier (TIA) with an InGaAs/InP PIN photodiode using a recently developed self-aligned wafer-level integration technology (SAWLIT), operation at 10 Gb/s is achieved. The CMOS transimpedance amplifier exhibits a transimpedance gain of 51 dBOmega and a bandwidth of 6.1 GHz.

On the study of parylene-N for millimeter-wave integrated circuits

In this work Parylene-N is investigated as a passivation layer for microwave and millimeter-wave integrated circuits (MMIC). The electrical and mechanical properties of this material show great potential for various applications in integrated circuits especially at higher frequencies. For the first time, Parylene-N has been used as a passivation layer on different test structures and their performance is studied up to 40GHz. The measurement results obtained from ring resonators and Coplanar Waveguide (CPW) transmission lines before and after passivation show that a 10 μm thick Parylene-N layer increases the insertion loss by only a negligible amount (0.007dB/mm at 40GHz), while a 5 μm thick coating does not have any influence on the insertion loss, confirming that the loss tangent of this coating material is very low. Besides, in measuring the resonance frequencies of different ring resonators a frequency shift of less than 1% is observed with a 10 μm passivation at 40GHz, while the shift is less than 0.05% for a 5 μm thickness, indicating a very low dielectric constant. In this paper we also show the performance of a multi-layer structure using a Coplanar Waveguide (CPW) vertical transition with vias etched between two Parylene-N layers. The results demonstrate the ability to use this flexible material as a low loss multi-layer substrate for microwave frequency applications. Finally a humidity study is performed by employing an array of dewpoint sensors with 10 μm thick Parylene-N coating. Hence the Mean Time to Failure (MTTF) under different humidity and temperature conditions is derived. Results indicate that Parylene-N is a good candidate as an encapsulant for MMIC applications.

1.3–1.55-

A heterogeneous 10-Gb/s 1.3- to 1.55-mum optoelectronic receiver is designed and fabricated using a complementary metal-oxide-semiconductor transimpedance amplifier and an InGaAs-InP PIN (p-type, intrinsic, n-type diode) photodiode. The receiver is heterogeneously integrated based on a batch fabrication process which promises low fabrication cost. The receiver measures a transimpedance gain of higher than 50 dBldrOmega over a bandwidth of 6 GHz and demonstrates an open eye diagram with a 1.55-mum 10-Gb/s light source.

\mu

A three dimensional low noise amplifier using post-processed transmission lines on a 130nm CMOS technology is presented. A 15µm thick low-k and low-loss Parylene-N layer is used to elevate transmission lines from the lossy Si substrate. This reduces the attenuation per unit length of the transmission lines by about 60%, while preserves CMOS chip area (in this specific design) by approximately 25% that is otherwise dedicated to these lines. The 3D amplifier measures a gain of 13dB at 2GHz with 3dB bandwidth of 500MHz, noise figure of 3.3dB and output 1dB compression point of +4.6dBm. With a simple room temperature CMOS compatible post-fabrication process, smaller chips with better performances are achieved. It is also shown that accurate simulation of a 3D circuit is attained by considering various parasitic effects that exist in this type of implementation.