Rosa R. Lahiji

Characterization of Parylene-N as Flexible Substrate and Passivation Layer for Microwave and Millimeter-Wave Integrated Circuits

Investigation of Parylene-N (Pa-N) as a flexible substrate, multilayer dielectric material, and passivation layer for microwave and millimeter-wave integrated circuits is presented. For the first time, the electrical properties of Parylene-N have been characterized up to 60 GHz using various microstrip ring resonators and transmission lines. As a flexible substrate, Parylene-N measures a nearly invariant relative dielectric constant (epsivr) of 2.35-2.4, and a loss tangent (tan delta) of lower than 0.0006 for frequencies up to 60 GHz. Because of the above properties, as a passivation layer, Parylene-N causes insignificant modifications to the properties of underlying passive and active structures. Measurement of coplanar waveguide transmission lines before and after passivation reveals that a 5-mum Parylene-N barely changes the insertion loss (below measurement accuracy) while a 10-mum-thick Parylene-N layer increases the insertion loss by only 0.007 dB/mm (below measurement error) at 40 GHz. Ring resonators before and after a 5 or 10 mum passivation show a frequency shift of less than 0.05% or 1.51%, respectively, up to 40 GHz. The influence of Parylene-N passivation on the RF performance of GaAs MESFETs is also found to be negligible. Finally, humidity studies with dew point sensors reveal that with a 10- mum-thick passivation at 25degC and 100% relative humidity, the MTTF is about 481.6 days. In summary, the results indicate that Parylene-N is an excellent and promising material for application at microwave and millimeter-wave frequencies.

Multiwafer vertical interconnects for three-dimensional integrated circuits

Low-loss multiwafer vertical interconnects appropriate for a microstrip-based circuit architecture are proposed. These transitions have been designed, fabricated, and measured for 100-mum-thick silicon and GaAs substrates separately. Experimental results show excellent performance up to 20 GHz, with extremely low insertion loss (better than 0.12 and 0.38 dB for the two different silicon designs and 0.2 dB for the GaAs transition), and very good return loss (reflection of better than 12.9 and 17.3 dB for the two silicon designs, respectively, and 13.6 dB for the GaAs design). Using a high-performance transition allows for a more power-efficient interconnect, while it enables denser packaging by stacking the substrates on top of each other, as todays technologies demand

3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

Parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15-¿ m-thick parylene-N layer and 0.56 dB/mm for a 50-¿ CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with under passes that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13-¿m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of +4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.

A headband for classifying human postures

a real-time method using only accelerometer data is developed for classifying basic human static postures, namely sitting, standing, and lying, as well as dynamic transitions between them. The algorithm uses discrete wavelet transform (DWT) in combination with a fuzzy logic inference system (FIS). Data from a single three-axis accelerometer integrated into a wearable headband is transmitted wirelessly, collected and analyzed in real time on a laptop computer, to extract two sets of features for posture classification. The received acceleration signals are decomposed using the DWT to extract the dynamic features; changes in the smoothness of the signal that reflect a transition between postures are detected at finer DWT scales. FIS then uses the previous posture transition and DWT-extracted features to determine the static postures.

A high-voltage, high-current CMOS pulse generator ASIC for deep brain stimulation

A high-voltage, high-current pulse generator ASIC based on 0.35-εm high-voltage CMOS technology is presented. The chip has eight independently-controlled biphasic output channels that can generate either current- or voltage-controlled pulses. The output driver is capable of delivering current up to 1.26 mA or 5.04 mA and voltage up to 2.36 V or 9.45 V; all with 6-bit resolution. The stimulation frequency can be adjusted between 3 Hz to 5 kHz, while pulse width can vary from 20 µs to 640 εs in 20 εs steps for 100-kHz clock frequency. The timing parameters can be adjusted further by varying the clock frequency. These parameters, including pulse phase, can be programmed independently in each channel to allow different waveform generation. The foregoing provides an on-chip solution for an arbitrary function generator that can be monolithically fabricated with the rest of the circuitry. Based on its configuration this chip is an ideal solution for deep brain stimulation (DBS) electrode for targeted stimulation through current steering.

Low-Loss Coplanar Waveguide Transmission Lines and Vertical Interconnects on Multi-Layer Parylene-N

Coplanar waveguide transmission lines and vertical interconnects are implemented on a thick (15µm) Parylene-N dielectric layer over a lossy CMOS-grade Si substrate. Devices are measured up to 40GHz and show very low loss behavior. Low loss tangent and low dielectric constant characteristics of Parylene-N result in significant improvement of transmission lines and interconnects compared to those implemented in a standard Si integrated circuit technology.

A Distributed Analogue CMOS Phase Shifter with Shielded Transmission Line

A novel wideband analogue phase shifter using shielded transmission line and slow-wave Coplanar Waveguide (CPW) is implemented using CMOS 130 nm technology. With no power consumption and a compact length of 1 mm the phase shifter has the capability of generating a phase difference of about 60deg at 10 GHz, where the insertion loss varies from -2.6 dB at -1.5V to -3.8 dB at 1.5 V. The design has been characterized up to 40 GHz and demonstrates competitive capabilities in terms of performance, size, control voltage and linearity with the state of the art CMOS distributed analogue phase shifters. Linearity measurements reveal that the 1-dB compression point at 10 GHz is about +14.7 dBm. This design shows the opportunities existing for monolithically integration of a low loss and compact phase shifter in CMOS technology.

On the study of parylene-N for millimeter-wave integrated circuits

In this work Parylene-N is investigated as a passivation layer for microwave and millimeter-wave integrated circuits (MMIC). The electrical and mechanical properties of this material show great potential for various applications in integrated circuits especially at higher frequencies. For the first time, Parylene-N has been used as a passivation layer on different test structures and their performance is studied up to 40GHz. The measurement results obtained from ring resonators and Coplanar Waveguide (CPW) transmission lines before and after passivation show that a 10 μm thick Parylene-N layer increases the insertion loss by only a negligible amount (0.007dB/mm at 40GHz), while a 5 μm thick coating does not have any influence on the insertion loss, confirming that the loss tangent of this coating material is very low. Besides, in measuring the resonance frequencies of different ring resonators a frequency shift of less than 1% is observed with a 10 μm passivation at 40GHz, while the shift is less than 0.05% for a 5 μm thickness, indicating a very low dielectric constant. In this paper we also show the performance of a multi-layer structure using a Coplanar Waveguide (CPW) vertical transition with vias etched between two Parylene-N layers. The results demonstrate the ability to use this flexible material as a low loss multi-layer substrate for microwave frequency applications. Finally a humidity study is performed by employing an array of dewpoint sensors with 10 μm thick Parylene-N coating. Hence the Mean Time to Failure (MTTF) under different humidity and temperature conditions is derived. Results indicate that Parylene-N is a good candidate as an encapsulant for MMIC applications.

Design and implementation of a novel three dimensional CMOS low noise amplifier with transmission lines on parylene-N

A three dimensional low noise amplifier using post-processed transmission lines on a 130nm CMOS technology is presented. A 15µm thick low-k and low-loss Parylene-N layer is used to elevate transmission lines from the lossy Si substrate. This reduces the attenuation per unit length of the transmission lines by about 60%, while preserves CMOS chip area (in this specific design) by approximately 25% that is otherwise dedicated to these lines. The 3D amplifier measures a gain of 13dB at 2GHz with 3dB bandwidth of 500MHz, noise figure of 3.3dB and output 1dB compression point of +4.6dBm. With a simple room temperature CMOS compatible post-fabrication process, smaller chips with better performances are achieved. It is also shown that accurate simulation of a 3D circuit is attained by considering various parasitic effects that exist in this type of implementation.

Low loss multi-wafer vertical interconnects for three dimensional integrated circuits

A low loss multi-wafer vertical interconnect appropriate for a microstrip-based circuit architecture is proposed. This transition has been designed, fabricated and measured on 100 /spl mu/m thick GaAs substrates. The measurements demonstrate insertion loss of better than 0.2dB and reflection of better than 13.6dB up to 20GHz. Using such a high performance transition allows for a more power efficient interconnect, while it enables denser packaging by stacking the substrates on top of each other, as todays technologies demand.