Haseok Jeon

Solution-processed InGaZnO-based thin film transistors for printed electronics applications

This letter reports the utility of using the sol-gel process for exploring the library of multicomponent ZnO-based oxides as an active layer of thin film transistors. We chose InGaZnO as a starting material and modulated the Ga content to examine the potential of this material. Increasing the Ga ratio from 0.1 to 1 brought about a dynamic shift in the electrical behavior from conductor to semiconductor. This exploratory work critically helped us fabricate a device with robust device performance (a mobility of 1∼2 cm2 V−1 s−1 for the 400 °C-sintered samples and 0.2 cm2 V−1 s−1 for the 300 °C-sintered samples).

Thermal stability of metal Ohmic contacts in indium gallium zinc oxide transistors using a graphene barrier layer

The excellent impermeability of graphene was exploited to produce stable ohmic contact at the interface between Al metal and a semiconducting indium gallium zinc oxide (IGZO) layer after high-temperature annealing. Thin film transistors (TFTs) were fabricated with and without a graphene interlayer between the Al metal and the IGZO channel region. Metal contact at the interface prepared without a graphene interlayer showed serious instabilities in the IGZO TFT under thermal annealing; however, the insertion of a graphene interlayer between the IGZO channel and the Al metal offered good stability under repeated high-temperature annealing cycles and maintained ohmic contact.

Effects of Substrate Heating on the Amorphous Structure of InGaZnO Films and the Electrical Properties of Their Thin Film Transistors

This study examines the effects of substrate heating on the amorphous structure of InGaZnO4 (IGZO) films and the device performance of transistors produced from these films. By combining high-resolution transmission electron microscopy (HRTEM) and energy-filtered selected area electron diffraction (EF-SAED), we found that the atomic order improved significantly for the IGZO films deposited on a heated substrate, compared to the samples deposited on an unheated substrate and postannealed. Measurement of the electrical characteristics of the transistors discloses that the amorphous structure changes induced by substrate heating profoundly influenced the overall device performance, leading to a substantial increase in electron mobility.

A Study on the Breakdown Mechanism of an Electroless-Plated Ni(P) Diffusion Barrier for Cu/Sn/Cu 3D InterconnectBonding Structures

This study examined the thermal stability of an electroless-plated Ni(P) barrier layer inserted between Sn and Cu in the bonding structure of Cu/Sn/Cu for three-dimensional (3D) interconnect applications. A combination of transmission electron microscopy (TEM) and scanning electron microscopy allowed us to fully characterize the bonding morphology of the Cu/Ni(P)/Sn/Ni(P)/Cu joints bonded at various temperatures. The barrier suppressed Cu and Sn interdiffusion very effectively up to 300°C; however, an interfacial reaction between Ni(P) and Sn led to gradual decomposition into Ni3P and Ni3Sn4. Upon 350°C bonding, the interfacial reaction brought about complete disintegration of the barrier in local areas, which allowed unhindered interdiffusion between Cu and Sn.

Effects of Post Annealing on the Electrical Properties of ZnO Thin Films Transistors

This paper reports the effects of post-annealing of ZnO thin films on their microstructure and the device performance of the transistors fabricated from the films. From X-ray diffraction and transmission electron microscopy characterization, we uncovered that the grain size increased with the annealing temperature escalating and that the film stress shifted from compressive to tensile due to the grain size increment. Electrical characterization revealed that the grain size increase damaged the device performance by drastically lifting the off-current level. By annealing the devices in an ambient (instead of air), we were able to suppress the off-current while improving the electron mobility.