Hyoungsub Kim

High-mobility and low-power thin-film transistors based on multilayer MoS2 crystals

Unlike graphene, the existence of bandgaps (1-2 eV) in the layered semiconductor molybdenum disulphide, combined with mobility enhancement by dielectric engineering, offers an attractive possibility of using single-layer molybdenum disulphide field-effect transistors in low-power switching devices. However, the complicated process of fabricating single-layer molybdenum disulphide with an additional high-k dielectric layer may significantly limit its compatibility with commercial fabrication. Here we show the first comprehensive investigation of process-friendly multilayer molybdenum disulphide field-effect transistors to demonstrate a compelling case for their applications in thin-film transistors. Our multilayer molybdenum disulphide field-effect transistors exhibited high mobilities (>100 cm(2) V(-1) s(-1)), near-ideal subthreshold swings (~70 mV per decade) and robust current saturation over a large voltage window. With simulations based on Shockleys long-channel transistor model and calculations of scattering mechanisms, these results provide potentially important implications in the fabrication of high-resolution large-area displays and further scientific investigation of various physical properties expected in other layered semiconductors.

Germanium nanowire field-effect transistors with SiO2 and high-κ HfO2 gate dielectrics

Single-crystal Ge nanowires are synthesized by a low-temperature (275 °C) chemical vapor deposition (CVD) method. Boron doped p-type GeNW field-effect transistors (FETs) with back-gates and thin SiO2 (10 nm) gate insulators are constructed. Hole mobility higher than 600 cm2/V s is observed in these devices, suggesting high quality and excellent electrical properties of as-grown Ge wires. In addition, integration of high-κ HfO2 (12 nm) gate dielectric into nanowire FETs with top-gates is accomplished with promising device characteristics obtained. The nanowire synthesis and device fabrication steps are all performed below 400 °C, opening a possibility of building three-dimensional electronics with CVD-derived Ge nanowires.

Effects of hydroxyl groups in polymeric dielectrics on organic transistor performance

Polymeric dielectrics having different ratios of hydroxyl groups were intentionally synthesized to investigate the effect of hydroxyl groups on the electrical properties of pentacene-based organic thin film transistors (OTFTs). Large hysteresis usually observed in OTFT devices was confirmed to be strongly related to the hydroxyl bonds existing inside of polymeric dielectrics and could be reduced by substituting with cinnamoyl groups. Although the hydroxyl groups deteriorate the capacitance-voltage characteristics and gate leakage current densities, exceptionally high hole mobility (5.5cm2V−1s−1) could be obtained by increasing the number of hydroxyl groups, which was not caused by the improvement of pentacene crystallinity but related to the interface characteristics.

Effects of crystallization on the electrical properties of ultrathin HfO2 dielectrics grown by atomic layer deposition

Microstructural evolution and resulting changes in electrical properties of atomic-layerdeposition-grown HfO2 on SiO2/Si substrates were studied as a function of annealing temperature in a N2 ambient. As deposited ∼30-A-thick HfO2 on 15 and 25 A thermal SiO2 were almost entirely amorphous, although a low density of crystalline seeds were observed and crystallization occurred from these nuclei during furnace anneals at temperatures >∼500 °C. The major crystalline phase thus formed was monoclinic, and some fraction of tetragonal phase was observed during crystallization according to transmission electron microscopy electron diffraction analysis. Complete crystallization occurred around 700 °C and, at higher temperatures, significant interfacial silicon dioxide growth was observed due to the presence of a small partial pressure of oxygen in the annealing ambient. No significant increase of leakage current in the trap-assisted tunneling conduction regime was observed during the intermediate and final stage of...

Interfacial characteristics of HfO2 grown on nitrided Ge (100) substrates by atomic-layer deposition

The microstructural and electrical properties of Ge-based metal–oxide–semiconductor capacitors containing high-k gate dielectric layers were investigated with and without the presence of a GeOxNy interface layer. The effect of this nitrided layer on thermal stability of the metal oxide/Ge structures was probed by medium energy ion energy spectroscopy (MEIS). Atomic-layer deposited HfO2 on a chemical oxide-terminated Ge (100) surface exhibited poor capacitance–voltage behavior; however, direct substrate surface nitridation at 600°C in NH3 ambient before HfO2 deposition improved the carrier trapping characteristics. Diffusion of metal impurities (including Hf) into the interfacial oxide/Ge-substrate may be an important source of the measured degradation of electrical properties. MEIS results suggested that the GeOxNy interface layer may inhibit Hf diffusion into the underlying semiconductor at the temperatures investigated.

A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate

A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.

Atomic layer deposition of ZrO2 on W for metal–insulator–metal capacitor application

A metal–insulator–metal (MIM) capacitor using ZrO2 on tungsten (W) metal bottom electrode was demonstrated and characterized in this letter. Both ZrO2 and W metal were synthesized by an atomic layer deposition (ALD) method. High-quality 110∼115 A ZrO2 films were grown uniformly on ALD W using ZrCl4 and H2O precursors at 300 °C, and polycrystalline ZrO2 in the ALD regime could be obtained. A 13∼14-A-thick interfacial layer between ZrO2 and W was observed after fabrication, and it was identified as WOx through angle-resolved x-ray photoelectron spectroscopy analysis with wet chemical etching. The apparent equivalent oxide thickness was 20∼21 A. An effective dielectric constant of 22∼25 including an interfacial WOx layer was obtained by measuring capacitance and thickness of MIM capacitors with Pt top electrodes. High capacitance per area (16∼17 fF/μm2) and low leakage current (10−7 A/cm2 at ±1 V) were achieved.

Local epitaxial growth of ZrO2 on Ge (100) substrates by atomic layer epitaxy

High-k dielectric deposition processes for gate dielectric preparation on Si surfaces usually result in the unavoidable and uncontrolled formation of a thin interfacial oxide layer. Atomic layer deposition of ∼55-A ZrO2 film on a Ge (100) substrate using ZrCl4 and H2O at 300 °C was found to produce local epitaxial growth [(001) Ge//(001) ZrO2 and [100] Ge//[100] ZrO2] without a distinct interfacial layer, unlike the situation observed when ZrO2 is deposited using the same method on Si. Relatively large lattice mismatch (∼10%) between ZrO2 and Ge produced a high areal density of interfacial misfit dislocations. Large hysteresis (>200 mV) and high frequency dispersion were observed in capacitance–voltage measurements due to the high density of interface states. However, a low leakage current density, comparable to values obtained on Si substrates, was observed with the same capacitance density regardless of the high defect density.

Assessment of silicon MOS and carbon nanotube FET performance limits using a general theory of ballistic transistors

A simple model for ballistic nanotransistors, which extends previous work by treating both the charge control and the quantum capacitance limits of MOSFET-like transistors, is presented. We apply this new model to MOSFET-like carbon nanotube FETs (CNTFETs) and to MOSFETs at the scaling limit. The device physics for operation at ballistic and quantum capacitance limits are explored. Based on the analysis of recently reported CNTFETs, we compare CNTFETs to MOSFETs. The potential performance advantages over Si that might be achieved at the scaling limit are established by using the new model.

Spinodal decomposition in amorphous metal-silicate thin films: Phase diagram analysis and interface effects on kinetics

Among several metal silicate candidates for high permittivity gate dielectric applications, the mixing thermodynamics of the ZrO2–SiO2 system were analyzed, based on previously published experimental phase diagrams. The driving force for spinodal decomposition was investigated in an amorphous silicate that was treated as a supercooled liquid solution. A subregular model was used for the excess free energy of mixing of the liquid, and measured invariant points were adopted for the calculations. The resulting simulated ZrO2–SiO2 phase diagram matched the experimental results reasonably well and indicated that a driving force exists for amorphous Zr–silicate compositions between ∼40 mol % and ∼90 mol % SiO2 to decompose into a ZrO2-rich phase (∼20 mol % SiO2) and SiO2-rich phase (>98 mol % SiO2) through diffusional phase separation at a temperature of 900 °C. These predictions are consistent with recent experimental reports of phase separation in amorphous Zr–silicate thin films. Other metal–silicate systems...