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Hashemi Pouya

IBM

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Publication

Featured researches published by Hashemi Pouya.

Archive | 2017

High density programmable e-fuse co-integrated with vertical FETs

Balakrishnan Karthik; Guillorn Michael A; Hashemi Pouya; Reznicek Alexander

Archive | 2017

METHOD AND STRUCTURE FOR INCORPORATING STRAIN IN NANOSHEET DEVICES

Balakrishnan Karthik; Cheng Kangguo; Hashemi Pouya; Reznicek Alexander

Archive | 2017

VERTICAL TRANSISTOR STRUCTURE WITH REDUCED PARASITIC GATE CAPACITANCE

Balakrishnan Karthik; Cheng Kangguo; Hashemi Pouya; Reznicek Alexander

Archive | 2017

METHODS FOR FORMING HYBRID VERTICAL TRANSISTORS

Balakrishnan Karthik; Cheng Kangguo; Hashemi Pouya; Reznicek Alexander

Archive | 2017

TENSILE STRAINED NFET AND COMPRESSIVELY STRAINED PFET FORMED ON STRAIN RELAXED BUFFER

Balakrishnan Karthik; Fogel Keith E; Hashemi Pouya; Reznicek Alexander

Archive | 2016

Lateral Bipolar Junction Transistor With Multiple Base Lengths

Balakrishnan Karthik; Hashemi Pouya; Ning Tak H; Reznicek Alexander

Archive | 2018

MASK-PROGRAMMABLE ROM USING A VERTICAL FET INTEGRATION PROCESS

Balakrishnan Karthik; Hashemi Pouya; Ning Tak H; Reznicek Alexander

Archive | 2018

INTEGRATED FERROELECTRIC CAPACITOR/ FIELD EFFECT TRANSISTOR STRUCTURE

Ando Takashi; Hashemi Pouya; Reznicek Alexander

Archive | 2018

Structure containing first and second vertically stacked nanosheets having different crystallographic orientations

Balakrishnan Karthik; Cheng Kangguo; Hashemi Pouya; Reznicek Alexander

Archive | 2018

METHOD OF JUNCTION CONTROL FOR LATERAL BIPOLAR JUNCTION TRANSISTOR

Hashemi Pouya; Lee Kam Leung; Ning Tak H; Yau Jeng Bang

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Collaboration

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Reznicek Alexander

IBM

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Balakrishnan Karthik

IBM

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Cheng Kangguo

IBM

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Ando Takashi

IBM

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Ning Tak H

IBM

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Guillorn Michael A

IBM

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Narayanan Vijay

IBM

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Fogel Keith E

IBM

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Lee Choonghyun

IBM

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Bedell Stephen W

IBM

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