Hayssam El-Razouk

Low power multipliers based on new hybrid full adders

Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8x8 implementation, the ALL-NAND array multiplier achieves 15.7% and 7.8% reduction in power consumption and transistor count at the cost of a 6.9% increase in time delay compared to standard array multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and transistor count by 12.5% and 7.3%, respectively, with a 4.4% longer time delay, compared to conventional tree multiplier.

New Implementations of the WG Stream Cipher

This paper presents two new hardware designs of the Welch-Gong (WG)-128 cipher, one for the multiple output WG (MOWG) version, and the other for the single output version WG based on type-II optimal normal basis representation. The proposed MOWG design uses signal reuse techniques to reduce hardware cost in the MOWG transformation, whereas it increases the speed by eliminating the inverters from the critical path. This is accomplished through reconstructing the key and initial vector loading algorithm and the feedback polynomial of the linear feedback shift register. The proposed WG design uses properties of the trace function to optimize the hardware cost in the WG transformation. The application-specific integrated circuit and field-programmable gate array implementations of the proposed designs show that their areas and power consumptions outperform the existing implementations of the WG cipher.

A New Transistor-Redundant Voter for Defect-Tolerant Digital Circuits

As CMOS technology is being scaled down aggressively towards the nano-regime, digital circuits are becoming more and more prone to failure, not only because of transient faults, but more likely as a result of permanent defects. This paper presents a new technique for defect-tolerance at the transistor level called transistor redundancy (TR); targeting the voter design in fault-tolerant systems. This is the first time transistor redundancy is used to design the first defect-tolerant voter circuit. TR allows the masking of faults resulting from permanent defects, since it uses redundant transistors to implement the functionality of each transistor. Circuit simulations of n-bit TR-voter based triple modular redundancy (TMR) adder were conducted and the results were compared with conventional-voter based TMR adder. The use of the proposed TR-voter gives 100% fault masking capabilities (considering the single fault scenario) compared to fault-intolerant conventional-voter that does not mask any defect. There was no increase in the time delay but the total number of transistor, for each adder, increased by 25% compared to conventional TMR

New designs of signed multipliers

Two new architectures for signed multiplication for array and tree topologies are presented. The signed array multiplier is based on the new low power high speed adders, and achieves 15% and 30% reduction in time-delay and power consumption compared to Baugh Wooleys. The proposed tree multiplier incorporates two new low-power (4:2) compressors, capable of handling negative weights, and achieves 10% and 19% reduction in time-delay and power consumption compared to Wallace multiplier.

New designs of 14-transistor PPM adder

In this paper, we propose improved designs of full adders, known as plus-plus-minus (PPM) adders, for redundant binary (RB) number systems applications. The proposed two PPM adder designs use 14 transistors and are derived from new algorithms. They achieve reduction in the time delay, power consumption, and chip area, compared to currently available designs. Furthermore, the proposed 14-transistor adders have been used to build two efficient designs of on-line radix-2 redundant multipliers. All the proposed designs have been implemented using 0.18 mum CMOS technology. The implementation results show that the proposed PPM adders have significant reduction in both power consumption and time delay compared to the 24-transistor PPM adder

New Hardware Implementationsof WG and WG- StreamCiphers Using Polynomial Basis

The WG stream ciphers are based on the WG (Welch-Gong) transformation and possess proved randomness properties. In this paper we propose nine new hardware designs for the two classes of WG(29,11) and WG-16. For each class, we design and implement three versions of standard, pipelined and serial. For the first time, we use the polynomial basis (PB) representation to design and implement the WG(29,11) and WG-16. We consider traditional PB multiplier for the WG(29,11), and, the traditional and Karatsuba multipliers for the WG-16. For efficient field operations, we propose an irreducible trinomial for the WG(29,11). For the WG-16, a new formulation of its permutation which requires only 8 multipliers is introduced. In these designs, the multipliers in the transforms arefurther reduced by utilizing a novel computation for the trace of the multiplication of two field elements. We have implemented theproposed designs in ASIC using CMOS 65 nm technology. The results show that the proposed standard WG(29,11) consumes less area and slightly enhances the normalized throughput, compared to the existing counterparts. For the WG-16, throughput of theproposed pipelined instance outperforms the previous designs. Moreover, the speed of the proposed WG-16 designs meet the peak bit rates for the 4 G specifications.

Area and Power Efficient Array and Tree Multipliers

New circuit implementations of the partial product generators (PP), for array and tree architectures, are presented in this paper. They require less number of transistors and consequently resulting in a smaller area and less power dissipation. The realization of 8times8 array multipliers based on our new low power low area PP implementations achieved 17% and 13.3% reduction in power consumption and transistor count respectively compared to Baugh Wooleys. The tree multiplier, based on our new PP units, achieved 15.4% and 9.4% reduction in power consumption and transistor counts compared to Wallace multiplier

A New Multiplicative Inverse Architecture in Normal Basis Using Novel Concurrent Serial Squaring and Multiplication

Itoh and Tsujii proposed a fast algorithm for computing multiplicative inverses (inversions) over GF(2m) using normal bases by iterating single multiplications and cyclic shifts. Recently, the Itoh-Tsujii algorithm (ITA) has been modified to use two digit-level single multiplications. The improvements of the modified Itoh-Tsujii and its variant algorithms are based on reducing the computational latency at the expense of more area requirements. In this paper, we propose a new inversion architecture based on the classical IT algorithm (or improved one) utilizing a novel interleaved computations of two single multiplications and squarings at the digit-level. The new inverter outperforms previous modified Itoh-Tsujii algorithms (such as the Ternary Itoh-Tsujii and optimal 3-chain algorithms) in terms of its lower latency, higher throughput, and improved hardware efficiency. The efficiency of the proposed field inverter is demonstrated by comparisons based on application specific integrated circuits (ASIC) implementations results using the standard 65nm CMOS technology libraries.

New Bit-Level Serial GF (2^m) Multiplication Using Polynomial Basis

The Polynomial basis (PB) representation offers efficient hardware realizations of GF(2m) multipliers. Bit-level serial multiplication over GF(2m) trades-off the computational latency for lower silicon area, and hence, is favored in resource constrained applications. In such area critical applications, extra clock cycles might take place to read the inputs of the multiplication if the data-path has limited capacity. In this paper, we present a new bit-level serial PB multiplication scheme which generates its output bits in parallel after m clock cycles without requiring any preloading of the inputs, for the first time in the open literature. The proposed architecture, referred to as fully-serial-in-parallel-out (FSIPO), is useful for achieving higher throughput in resource constrained environments if the data-path for entering inputs has limited capacity, especially, for large dimensions of the field GF (2m).