Z. Abid

Low power multipliers based on new hybrid full adders

Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8x8 implementation, the ALL-NAND array multiplier achieves 15.7% and 7.8% reduction in power consumption and transistor count at the cost of a 6.9% increase in time delay compared to standard array multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and transistor count by 12.5% and 7.3%, respectively, with a 4.4% longer time delay, compared to conventional tree multiplier.

Low power n-bit adders and multiplier using lowest-number-of-transistor 1-bit adders

4-bit ripple carry adders (RCA), 12-bit carry select adders (CSA), and a 4times4 Braun multiplier, based on lowest-number-of-transistor full adders, were designed and simulated. The designed full adders consist of 10 transistors and were used for n-bit adders with output voltage levels having a maximum of one threshold voltage (Vr) degradation. The 10 transistors adder achieved a 43.68% reduction in the power dissipation compared to the standard CMOS-28T adder. Power consumption can be further reduced by using an extra stack transistor. A 12-transistor adder was also designed for low area array multipliers

Temperature dependent DC characteristics of an InP/InGaAs/InGaAsP HBT

We report the DC characteristics of n-p-n InP/InGaAs/InGaAsP HBTs which have a composite-collector structure designed to improve the breakdown and gain. The devices exhibit common-emitter current gain of greater than 8 for over 9 orders of magnitude of collector current and breakdown voltages greater than 10 V. The DC gain for a typical device decreases from 40 at room temperature to 8 at 90 K. Over the same temperature range the collector-current ideality factor increases from 1.04 to 1.46, and the base current ideality factor is 0.05 to 0.1 larger than these values. We suggest that the high collector-current ideality factor and the lower gain at the lower temperatures is due to the increasing importance of tunneling of current across the emitter-base junction. The devices with the InGaAs/InGaAsP composite-collector structure offer better common-base turn-on behavior than those with InGaAs/InP as the collector structure, without the breakdown behavior being compromised.<<ETX>>

Efficient CMOL Gate Designs for Cryptography Applications

This paper introduces new hybrid complementary metal-oxide-semiconductor (CMOS)-nano (CMOL) circuits for efficient implementation of cryptographic algorithms. The novelty of this study is to utilize two types of nanojunction devices with CMOS to build the crypto IC. In particular, efficient XOR gate with resistive junctions and XOR/AND gates with diode-like junctions are develop to be used as building blocks of the corresponding modules of the Advanced Encryption Standard (AES) crypto IC. They allow a reduction of 79%, 43%, and 53% in power dissipation, area, and time delay compared to the existing CMOL implementation of AES system. When compared to field-programmable nanowire interconnect (FPNI) design of AES, a 56% increase in power dissipation was recorded in order to achieve a 92% and 15% reduction in area and time delay. This proposed circuit study also leverages the recent fabrication results, which is a feasible CMOS-nano hybrid solution for future crypto IC development.

New parallel multipliers based on low power adders

Two new parallel multiplier architectures are designed based on two new full adders. These two adders are based on a new algorithm and display low power dissipation and high speed. The compactness and regularity of conventional array multipliers are maintained. The partial products are generated more efficiently using lower number of transistors. The proposed two multipliers offer significant improved performance, in terms of speed and power dissipation, than standard array multipliers

Hysteresis in the switching of hot electrons in InP/InGaAs double‐heterojunction bipolar transistors

The switching behavior of a composite‐collector InP/InGaAs heterojunction bipolar transistor is found to be hysteretic at temperatures below 200 K. This arises from the underlying S‐shaped negative differential conductivity associated with the hot‐electron transport of electrons across the heterojunction barrier in the collector structure of such transistors.

Direct-Schottky-contact InP MESFET

The design and fabrication of an InP MESFET with excellent I-V characteristics are reported. A record high transconductance of 110 mS/mm was measured for a 1- mu m gate length direct-Schottky-contact InP MESFET, where the InP surface was not passivated or treated prior to the deposition of the gate contact. Microwave measurements show an f/sub max/ of 11.6 GHz for this typical nominal 1- mu m gate length device. A p-type planar doped layer was inserted between the buried n-type channel and the device surface at 18 nm from the gate metal. This planar layer enhances the Schottky barrier height and device performance.<<ETX>>

Current blocking in InP/InGaAs double heterostructure bipolar transistors

The one‐flux analysis of double‐heterostructure bipolar transistors with composite collectors in the preceding article W. R. McKinnon, J. Appl. Phys. 79, 2762 (1996) is compared to drift‐diffusion calculations and to measurements on InP/InGaAs/InP/composite collectors‐double heterostructure bipolar transistors. For quantitative agreement we include the effects of ionized impurities in the space‐charge regions, and an approximate treatment of Fermi–Dirac statistics.

A New Transistor-Redundant Voter for Defect-Tolerant Digital Circuits

As CMOS technology is being scaled down aggressively towards the nano-regime, digital circuits are becoming more and more prone to failure, not only because of transient faults, but more likely as a result of permanent defects. This paper presents a new technique for defect-tolerance at the transistor level called transistor redundancy (TR); targeting the voter design in fault-tolerant systems. This is the first time transistor redundancy is used to design the first defect-tolerant voter circuit. TR allows the masking of faults resulting from permanent defects, since it uses redundant transistors to implement the functionality of each transistor. Circuit simulations of n-bit TR-voter based triple modular redundancy (TMR) adder were conducted and the results were compared with conventional-voter based TMR adder. The use of the proposed TR-voter gives 100% fault masking capabilities (considering the single fault scenario) compared to fault-intolerant conventional-voter that does not mask any defect. There was no increase in the time delay but the total number of transistor, for each adder, increased by 25% compared to conventional TMR

Reduction of real-space transfer in depletion-mode dipole heterostructure field-effect transistors

The real space transfer in depletion‐mode dipole heterostructure field‐effect transistors (HFETs) has been investigated both theoretically and experimentally. Theoretically, we demonstrate that parallel conduction will be substantially reduced in the dipole HFET and to a smaller extent in the planar‐doped HFET when compared to the conventional HFET due to the increased carrier confinement. By measuring the cutoff frequency at various dc biases, the experimental results indicate that a reduced real space transfer effect occurs in the depletion‐mode dipole HFETs.