Hee-Cheol Choi

A 1.4 V 10-bit 20 MSPS pipelined A/D converter

A 1.4 V 10-bit 20 MSPS pipelined analog-to-digital converter was implemented using 0.25 /spl mu/m CMOS technology. The converter is based on low-voltage two-stage opamps and current reference generator for low-voltage operation. The current reference generator adopts a newly proposed dual-mode voltage booster that keeps the reference current constant regardless of temperature and voltage variations under the low-voltage environment. The ADC occupies a die area of 2.21 mm/sup 2/ (1700 /spl mu/m/spl times/1300 /spl mu/m) and dissipates 43 mW and 20 MHz clock rate with a 1.4 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.59 LSB and /spl plusmn/0.68 LSB, respectively.

A 15mW 0.2mm/sup 2/ 50MS/s ADC with wide input range

A 10b 50MS/s pipelined ADC, implemented in a 0.13mum CMOS process, consumes of 15mW and occupies an active die area of 0.2mm2 . In the prototype ADC, a high-to-low analog level-shifting SHA is proposed to deal with a wide input range of 2VPP differential. A PVT-insensitive bias generator is employed for low voltage operation. The measured DNL and INL are plusmn0.17LSB and plusmn0.16LSB, respectively

A calibration-free 3V 16b 500kS/s 6mW 0.5mm/sup 2/ ADC with 0.13 /spl mu/m CMOS

A calibration-free 3V 6mW 16-bit 500kS/s cyclic ADC with an active die area of 0.5mm/sup 2/ is implemented in a 0.13 /spl mu/m CMOS. The proposed converter adopts a 2.5-bit/stage cyclic architecture and capacitor layout scheme to achieve improved matching accuracy, the DNL and INL of /spl plusmn/0.90 LSB and /spl plusmn/6.1 LSB, respectively.