Jae-Whui Kim

A new level-up shifter for high speed and wide range interface in ultra deep sub-micron

A new level-up shifter aimed at ultra low core voltage and wide range I/O voltage is designed using a 90 nm CMOS process. The proposed level shifter uses analog circuit techniques and standard zero-Vt NMOS transistor without adding extra mask or process step. No static power consumption and stable duty ratio make this level shifter suitable for wide I/O interface voltage applications in ultra deep sub-micron. These techniques work even at 0.6 V core voltage, 1.65/spl sim/3.6V I/O voltage, within 45:55 duty ratio up to 200 MHz.

A slew-rate controlled output driver using PLL as compensation circuit

A slew rate controlled output driver adopting delay compensation method is implemented using 0.18 µm CMOS process for storage device interface. Phase-Locked Loop is used to generate compensation current and constant delay time. Compensation current reduces the slew rate variation over process, voltage and temperature variation in output driver. To generate constant delay time, the replica of VCO in PLL is used in output drivers slew rate control block. That reduces the slew rate variation over load capacitance variation. That has less 25% variation at slew rate than that of conventional output driver. The proposed output driver can satisfy UDMA100 interface which specify load capacitance as 15 ∼ 40pF and slew rate as 0.4 ∼ 1.0[V/ns].

A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter insensitive pulse generator (JIPG) circuit overcomes the degradation of SNR due to the feedback DAC clock jitter. The measured SNR and DR are 101 dB and THD is -94 dB.

A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS

A fully-differential zero-crossing-based 10b 26 MS/s pipelined ADC in a 65 nm CMOS process is presented. Switched-capacitor overshoot correction is compatible with the differential topology and allows faster operation. A CMFB is engaged in the coarse phase for constant common-mode. The 0.33 mm2 ADC achieves 54.3 dB SNDR with a FOM of 161 fJ/step.

A wide-band active-RC filter with a fast tuning scheme for wireless communication receivers

The paper presents the design of a wide-band active-RC filter with a fast tuning circuit for wireless communication receiver applications. The filter topology is the 5/sup th/-order Chebyshev-II lowpass filter type and the programmable bandwidth can be extended up to 10MHz while the stopband attenuation larger than 40dB is obtained. The successive approximation register (SAR) scheme is incorporated for a prompt on-chip tuning operation that should be needed for compensating RC variations. The filter is fabricated in a 0.18-/spl mu/m standard digital CMOS technology and dissipates 20.7mW for a supply voltage of 1.8V. The measured 3/sup rd/-order harmonic input intercept point (IIP3) is larger than 32dBm.

A 1 mW 10-bit 500KSPS SAR A/D converter

A 1mW 1.5 V 10-bit 500 KSPS successive approximation (SAR) analog-to-digital converter (ADC) was fabricated in a 0.25 um CMOS technology. The capacitive and resistive digital-to-analog converter (DAC) with a track and hold (T/H) function can operate with low power consumption at a high conversion rate using the modified operating timing control. The proposed high accuracy comparator with open loop and closed loop offset compensation techniques can operate at a low supply voltage. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are i 0.7 LSB and i 1.25 LSB, respectively. The total power consumption is 1 mW at a 500 KSPS conversion rate with a 1.5 V single supply voltage in measurement results.

A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current Converter

A 0.5-to-2GHz frequency synthesizer PLL implemented in a 90nm CMOS technology uses a 1.0V supply and dissipates 0.6 and 1.2mW while operating at 1 and 2GHz, respectively. The PLL occupies an active die area of 0.02mm2. The current-controlled method based on a self-biased voltage-to-current converter enables the use of a small size loop filter and makes the PLL bandwidth insensitive to PVT variations and multiplication factor.

A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture

This paper presents a high power efficient class-D audio power amplifier. The proposed class-D amplifier adopts the synchronized controlled oscillation modulator (SCOM), which is suitable for mobile applications. The THD+N at half the maximum output power is below 0.01% and the efficiency is better than 92% in an 8 /spl Omega/ speaker load. The one-chip integrated circuit is implemented in a 0.35 /spl mu/m CMOS technology, with a supply voltage range of 1.6 V-3.6 V. it occupies a chip area of 1.2/spl times/1.2 mm/sup 2/ and dissipates only 1.3 mA at idle.

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations

A slew-rate-controlled output driver having a constant transition time irrespective of environmental variations is described in this brief. The proposed output driver employs a capacitive feedback between the output and input of the driver to allow its transition time independent of process, voltage, temperature and output load variations. The proposed output driver was designed and fabricated using a 0.13-mum CMOS process. According to our experimental results, the normalized variation on transition time of the proposed output driver due to PVT variations was improved by 74%-80% as compared to the conventional output driver. The comparison result also indicates that the normalized variation on transition time due to output load change from 10 to 100 pF (10 times variation) in typical process, voltage and temperature corners was improved by up to 66%.

A new level shifter in ultra deep sub-micron for low to wide range voltage applications

A level shifter aimed at ultra low core voltage and wide range I/O voltage is designed using a 90nm CMOS process. Proposed level shifter uses analog circuit techniques and zero-Vt transistor with no extra process step, no static power and stable duty ratio make this level shifter suitable for ultra low core voltage and wide range I/O voltage applications. These techniques work even 0.6V core voltage, 1.65-3.6V I/O voltage within 45:55 duty ratio up to 200MHz.