Heejun Shim

Verification of CGRA Executable Code and Debugging of Memory Dependence Violation

We present verification and debugging of highly optimized executable code that is generated from C source code to run on CGRA (Coarse-Grained Reconfigurable Array). To generate the executable code, the CGRA compiler uses software pipelining technique that maps instructions in a loop body to multiple FUs (functional units) of CGRA for concurrent execution. Often, the programmer chooses to use aggressive optimization as a way to obtain highly performing executable code. For example, the programmer may turn off memory dependence check in order to suppress false dependence that would otherwise result in overly conservative, therefore poorly performing, executable code. A trouble is that it is not easy to verify correctness of the resulting executable code. In this paper, we propose a method to verify CGRA executable code and to detect memory dependence violation if there occurs such violation and to provide source code position where the violation occurs. We use the behavior of VLIW code as a reference and compare it with the behavior of CGRA code. In order to guide the comparison, compiler-generated mapping table information is used.

Simulation-based memory dependence checker for CGRA-mapped code verification

In a coarse-grained reconfigurable array (CGRA) architecture, software pipelining is primarily used to improve performance by exploiting loop-level parallelism (LLP). In this technique, the loop-carried memory dependence in user code prevents high parallelism, and it is difficult to be detected. In this paper, we propose a simulation-based memory dependence checker, which is used in the verification of CGRA-mapped code. We use as a reference the memory access behavior of the sequential processor and compare it to that of the CGRA-mapped code. Although it cannot guarantee perfect verification of memory dependence violations, our approach is useful by guiding the programmer to modify the source code. When a memory dependence violation is detected, our approach provides debugging information from the sequential compiled code. Moreover, our checker is implemented in the register transfer level; it enables verification time reduction and the testing of the CGRA-mapped code with a large test input stream in FPGA or ASIC implementations.