Hehua Zhang

Design and Optimization of Multiclocked Embedded Systems Using Formal Techniques

Todays system-on-chip and distributed systems are commonly equipped with multiple clocks. The key challenge in designing such systems is that two situations have to be captured and evaluated in a single framework. The first is the heterogeneous control-oriented and data-oriented behaviors within one clock domain, and the second is the asynchronous communications between two clock domains. In this paper, we propose to use timed automata and synchronous dataflow to model the dynamic behaviors of the multiclock train-control system, and a multiprocessor architecture for the implementation from our model to the real system. Data-oriented behaviors are captured by synchronous dataflow, control-oriented behaviors are captured by timed automata, and asynchronous communications of the interclock domain can be modeled as an interface timed automaton or a synchronous dataflow module. The behaviors of synchronous dataflow are interpreted by some equivalent timed automata to maintain the semantic consistency of the mixed model. Then, various functional properties that are important to guarantee the correctness of the system can be simulated and verified within the framework. We apply the framework to the design of a control system described in the standard IEC 61 375 and several bugs are detected. The bugs in the standard have been fixed, and the new version has been implemented and used in the real-world subway communication control system.

Design of Mixed Synchronous/Asynchronous Systems with Multiple Clocks

Todays distributed systems are commonly equipped with both synchronous and asynchronous components controlled with multiple clocks. The key challenges in designing such systems are (1) how to model multi-clocked local synchronous component, local asynchronous component, and asynchronous communication among components in a single framework. (2) how to ensure the correctness of model, and keep consistency between the model and the implementation of real system. In this paper, we propose a novel computation model named GalsBlock for the design of multi-clocked embedded system with both synchronous and asynchronous components. The computation model consists of several hierarchical compound and atom blocks communicating with data port connections. Each atom block can be refined as parallel mealy automata. The synchronous component can be captured in an atom block with the corresponding local control clock while the asynchronous component in an atom block without clock, and the asynchronous communications can be captured in the data port connections among blocks. The unified operational semantics and formal semantics are defined, which can be used for simulation and verification, respectively. Then, we can generate efficient VHDL code from the validated model, which can be synthesized into the FPGA processor for execution directly. We have developed the graphical modeling, simulation, verification, and code generation toolkit to support the computation model, and applied it in the design of a sub-system used in the real train communication control.

Bayesian-Network-Based Reliability Analysis of PLC Systems

Reliability analysis is an important part of safety critical programmable logic controller (PLC) systems. The complexity of PLC system reliability analysis arises in handling the complex relations among the hardware components and the embedded software. Different embedded software types will lead to different arrangements of hardware executions and different system reliability quantities. In this paper, we propose a novel probabilistic model, called the hybrid relation model (HRM), for the reliability analysis of PLC systems. Its construction is based upon the execution logic of the embedded software and the distribution of the hardware components. We prove the constructed HRM to be a Bayesian network (BN) that captures the execution logic of the embedded software. Then, we map the hardware components to the corresponding HRM nodes and embed the failure probabilities of the hardware components into the well-defined conditional probability distribution tables of the HRM nodes. With the computational mechanism of the BN, the HRM handles the failure probabilities of the hardware components as well as the complex relations caused by the execution logic of the embedded software. Experiment results demonstrate the accuracy of our model.

Modeling job shop scheduling with batches and setup times by timed Petri nets

Batch and setup times are two important factors in practical job shop scheduling. This paper proposes a method to model job shop scheduling problems including batches and anticipatory sequence-dependent setup times by timed Petri nets. The general modeling method is formally presented. The free choice property of the model is proved. A case study extracted from practical scheduling is given to show the feasibility of the modeling method. Comparison with some previous work shows that our model is more compact and effective in finding the best solution.

Uncertain Model and Algorithm for Hardware/Software Partitioning

Embedded systems are becoming increasingly popular due to their widespread applications. Hardware/software partitioning is becoming one of the most crucial steps in the design of embedded systems. The costs and delays of the final results of a design will strongly depend on partitioning. In this paper, we propose an uncertain programming model for partitioning problems. The delay related constraints and the cost related objective are modeled by uncertain variables with uncertainty distributions. We convert the uncertain programming model to a deterministic model and solve the converted model by an efficient heuristic method. We propose a heuristic based on genetic algorithm and simulated annealing to solve the problem near-optimally, even for quite large systems. Experiment results show that the proposed model and algorithm produce quality partitions.

An Effective Heuristic-Based Approach for Partitioning

As being one of the most crucial steps in the design of embedded systems, hardware/software partitioning has received more concern than ever. The performance of a system design will strongly depend on the efficiency of the partitioning. In this paper, we construct a communication graph for embedded system and describe the delay-related constraints and the cost-related objective based on the graph structure. Then, we propose a heuristic based on genetic algorithm and simulated annealing to solve the problem near optimally. We note that the genetic algorithm has a strong global search capability, while the simulated annealing algorithm will fail in a local optimal solution easily. Hence, we can incorporate simulated annealing algorithm in genetic algorithm. The combined algorithm will provide more accurate near-optimal solution with faster speed. Experiment results show that the proposed algorithm produce more accurate partitions than the original genetic algorithm.

Modeling and Analysis of Real-Life Job Shop Scheduling Problems by Petri nets

Real-life job shop scheduling problems are complex due to the needs of considering batches, setup times, transportation and parallel processing all together. This paper presents a method to model this kind of job shop scheduling problems by timed colored Petri nets. Two analysis methods including occurrence graph and simulation analysis for best makespan are proposed. Case studies are given to compare different modeling and analysis methods. Suggestions are proposed to select appropriate method for the scheduling problems in practice.

Symbolic Analysis of Programmable Logic Controllers

Programmable Logic Controllers (PLC) are widely used in industry. The reliability of the PLC is vital to many critical applications. This paper presents a novel approach to the symbolic analysis of PLC systems. The approach includes, (1) calculating the uncertainty characterization of the PLC system, (2) abstracting the PLC system as a Hidden Markov Model, (3) solving the Hidden Markov Model with domain knowledge, (4) combining the solved Hidden Markov Model and the uncertainty characterization to form a regular Markov model, and (5) utilizing probabilistic model checking to analyze properties of the Markov model. This framework provides automated analysis of both uncertainty calculations and performance measurements, without the need for expensive simulations. A case study of an industrial, automated PLC system demonstrates the effectiveness of our work.

System reliability calculation based on the run-time analysis of ladder program

Programmable logic controller (PLC) system is a typical kind of embedded system that is widely used in industry. The complexity of reliability analysis of safety critical PLC systems arises in handling the temporal correlations among the system components caused by the run-time execution logic of the embedded ladder program. In this paper, we propose a novel probabilistic model for the reliability analysis of PLC systems, called run-time reliability model (RRM). It is constructed based on the structure and run-time execution of the embedded ladder program, automatically. Then, we present some custom-made conditional probability distribution (CPD) tables according to the execution semantics of the RRM nodes, and insert the reliability probability of each system component referenced by the node into the corresponding CPD table. The proposed model is accurate and fast compared to previous work as described in the experiment results.

System Reliability Calculation Based on the Run-time Analysis of Ladder Program

Programmable logic controller (PLC) system, a typical member in the embedded family, is now widely applied in industry. For safety critical PLC systems, reliability is of top significance. However, due to subcomponents’ temporal correlations caused by the run-time execution of embedded ladder programs, the complexity of reliability analysis is greatly increased. In this paper, we propose a novel probabilistic model to analyze reliability of PLC systems, called run-time reliability model (RRM). RRM is automatically constructed based on the structure and run-time execution of the embedded ladder program. Moreover, it is also a dynamic bayesian network (DBN) capturing full dependencies in a PLC system. Then, according to execution semantics of RRM nodes, we present customized conditional probability distribution (CPD) tables to calculate final reliability of the system, with failure probability of every referenced component as refinement. The strength of this model is that not only does it explicitly specify the correlations between run-time execution of embedded software and system components, but also it serves as a computational mechanism for probabilistic inference. Besides, the proposed approach is superior to previous works in both accuracy and efficiency. Compared to monte carlo based simulation, the average error rate of reliability values inferred from RRM model is small.