Heiko O. Jacobs

Resolution and contrast in Kelvin probe force microscopy

The combination of atomic force microscopy and Kelvin probe technology is a powerful tool to obtain high-resolution maps of the surface potential distribution on conducting and nonconducting samples. However, resolution and contrast transfer of this method have not been fully understood, so far. To obtain a better quantitative understanding, we introduce a model which correlates the measured potential with the actual surface potential distribution, and we compare numerical simulations of the three-dimensional tip–specimen model with experimental data from test structures. The observed potential is a locally weighted average over all potentials present on the sample surface. The model allows us to calculate these weighting factors and, furthermore, leads to the conclusion that good resolution in potential maps is obtained by long and slender but slightly blunt tips on cantilevers of minimal width and surface area.

Practical aspects of Kelvin probe force microscopy

We discuss practical aspects of Kelvin probe force microscopy (KFM) which are important to obtain stable images of the electric surface potential distribution at high spatial resolution (<100 nm) and high potential sensitivity (<1 mV) on conducting and nonconducting samples. We compare metal-coated and semiconducting tips with respect to their suitability for KFM. Components of the metal coating can become detached during scanning, introducing sudden offset jumps in the potential maps (typically up to 350 mV between adjacent scan lines). However, n-doped silicon tips show no substantial tip alterations and, therefore, provide a stable reference during the experiment (offset jumps typically up to 40 mV between adjacent scan lines). These semiconducting tips must be electrically connected via contact pads. We use InGa and colloidal silver pads which are easily applied to the substrate supporting the cantilever and have a low enough differential contact resistance (350 Ω and 2.2 kΩ, respectively). Furthermor...

Surface potential mapping: A qualitative material contrast in SPM

Abstract Electric potential measurements on different metals and semiconductors have been performed using a scanning probe microscope. The measured potential shows a clear chemical contrast in all cases, allowing us to differentiate between different materials down to 100 nm in size with potential noise smaller than 1 mV. The lateral potential resolution as a function of the tip-sample distance has been measured and numerical calculations of the force density acting on the tip are presented along with theoretical examinations of the quantitative potential resolution.

Shape-and-solder-directed self-assembly to package semiconductor device segments

The self-assembly and packaging of integrated semiconductor device segments have been accomplished by combining geometrical shape recognition with site specific wetting and binding involving liquid solder. Components with complementary shapes were fabricated to recognize and encapsulate functional semiconductor devices. The components were suspended in water and agitated using a pulsating liquid flow. Two hundred AlGaN∕GaN light-emitting diodes with a chip size of 380×330 micrometers were assembled and packaged with a yield of 95% in 2min. The self-assembly procedure forms electrical interconnects between three-dimensionally shaped objects and provides a route to parallel assembly of hybrid microsystems.

Self-assembly of microscopic chiplets at a liquid–liquid–solid interface forming a flexible segmented monocrystalline solar cell

This paper introduces a method for self-assembling and electrically connecting small (20–60 micrometer) semiconductor chiplets at predetermined locations on flexible substrates with high speed (62500 chips/45 s), accuracy (0.9 micrometer, 0.14°), and yield (> 98%). The process takes place at the triple interface between silicone oil, water, and a penetrating solder-patterned substrate. The assembly is driven by a stepwise reduction of interfacial free energy where chips are first collected and preoriented at an oil-water interface before they assemble on a solder-patterned substrate that is pulled through the interface. Patterned transfer occurs in a progressing linear front as the liquid layers recede. The process eliminates the dependency on gravity and sedimentation of prior methods, thereby extending the minimal chip size to the sub-100 micrometer scale. It provides a new route for the field of printable electronics to enable the integration of microscopic high performance inorganic semiconductors on foreign substrates with the freedom to choose target location, pitch, and integration density. As an example we demonstrate a fault-tolerant segmented flexible monocrystalline silicon solar cell, reducing the amount of Si that is used when compared to conventional rigid cells.

Fluidic heterogeneous microsystems assembly and packaging

The nonrobotic fabrication of packaged microsystems that contain nonidentical parts has been accomplished by a directed self-assembly process. The self-assembly process uses geometrical shape recognition to identify different components and subsequent bond formation between liquid solder and metal-coated areas to form mechanical and electrical connections. We applied this concept of shape recognition and subsequent formation of contacts to assemble and package microsystems that contained nonidentical subunits. The self-assembly of three-component assemblies is demonstrated by sequentially adding device segments to the assembly solution including 200-mum-sized light-emitting diodes. Six hundred AlGaInP-GaAs light-emitting diode segments self-assembled onto device carriers in 2min without defects. Encapsulation units self-assembled onto the LED-carrier assemblies to form a three-dimensional (3-D) circuit path to operate the final device. The reported procedure provides a new route to the creation of autonomous heterogeneous microsystems including the realization of autonomous wireless sensor system that requires nonidentical units: CMOS circuitry, Non-CMOS sensor unit for sensing, III-V components for communication, and encapsulation units to form 3-D electrical interconnects. The creation of such systems is being discussed and a proof of concept experiment is being demonstrated

Integration of ZnO Microcrystals with Tailored Dimensions Forming Light Emitting Diodes and UV Photovoltaic Cells

This article reports a new integration approach to produce arrays of ZnO microcrystals for optoelectronic and photovoltaic applications. Demonstrated applications are n-ZnO/p-GaN heterojunction LEDs and photovoltaic cells. The integration process uses an oxygen plasma treatment in combination with a photoresist pattern on magnesium doped GaN substrates to define a narrow sub-100 nm width nucleation region. Nucleation is followed by lateral epitaxial overgrowth producing single crystal disks of ZnO with desired size over 2 in. wafers. The process provides control over the dimensions (<1% STD) and the location (0.7% STD pitch variation) of the ZnO crystals. The quality of the patterned ZnO is high; the commonly observed defect related emission in the electroluminescence spectra is completely suppressed, and a single near-band-edge UV peak is observed.

Biomimetic self-assembly of a functional asymmetrical electronic device

This paper introduces a biomimetic strategy for the fabrication of asymmetrical, three-dimensional electronic devices modeled on the folding of a chain of polypeptide structural motifs into a globular protein. Millimeter-size polyhedra—patterned with logic devices, wires, and solder dots—were connected in a linear string by using flexible wire. On self-assembly, the string folded spontaneously into two domains: one functioned as a ring oscillator, and the other one as a shift register. This example demonstrates that biomimetic principles of design and self-organization can be applied to generate multifunctional electronic systems of complex, three-dimensional architecture.

Single-chip CMOS anemometer

For the first time a packaged single-chip anemometry microsystem is reported. The system includes a thermal CMOS flow sensor with on-chip power management, signal conditioning, and A/D conversion. It is fabricated using an industrial IC process followed by post-CMOS micromachining. The system is packaged on a flexible substrate using flip-chip interconnection technology. The measurement of wind speeds is demonstrated in the range from 0 to 38 m/s (0 to 12 Beaufort), with a dynamic range of 65 dB. Total power consumption is 3 mW.

Measuring and modifying the electric surface potential distribution on a nanometre scale: a powerful tool in science and technology

The combination of atomic force microscopy (AFM) and Kelvin probe technology is a powerful tool to obtain high-resolution maps of the electric surface potential distribution on conducting and non-conducting samples. We show that potential maps of composite metal films and semiconductors show a clear chemical contrast and can be used to differentiate between different materials with a lateral resolution of a few 10 nm. Because AFM tips are not point-like structures, we establish a simple model to correlate the measured quantities with the true surface potential distribution, and compare numerical simulations of the three-dimensional tip-specimen model with experimental data from test structures. For the first time, we combine the electrostatic surface potential and the topography data to derive the local electrostatic field strength on active transistors. Using suitable substrates, trapped surface charges can be generated by applying short voltage pulses between the tip and the sample surface. These surface charges can be detected in the electric surface potential image and might be used as bits in new data storage systems or as target sites in self-assembly processes.