Heinrich Klar

A 2/spl mu/m Cmos Digital Adaptive Equalizer Chip For QAM Digital Radio Modems

IN HIGH-CAPACITY DIGITAL RADIO MODEMS employing multilevel quadrature modulation, adaptive time-domain equalizers are implemented to obtain the desired transmission performance. Toda , such equalizers are based on time-continous analog realizations , Fully digital implementation offers a number of important advantages such as stable and repeatable performance and lower cost, but challenges chip architecture and circuit technique to achieve the required data rate and computational complexity. In this paper the design and fabrication of a digital adaptive equalizer chip in CMOS technology will be described. Four of these chips have been used to implement a complex valued equalizer for QAM systems. The use of bit-level semi-systolic arrays as building blocks allows an effective implementation of the high speed portions of the chip. Because the chip set has to communicate with ECL chips (A/D converter and descrambler) and achieve low-power consumption, the inputs and outputs must be ECL-compatible. Synchronization on the between chips having different technology parameters, is a challenging condition, because worst case chips have t o communicate with best case chips. As shown in the block diagram of Figure 1, the digital adaptive equalizer chip contains a programmable nine-tap transversal filter, nine correlators, a cross channel adder (E), a programmable delay line (D) and a control logic block. The architecture of the transversal filter has been described*’ ’. This architecture, based on carry-save arithmetic, allows a small chip area and a high throughput rate independent of parameters like number of taps or wordlengths. In the correlators, the updating of coefficients is performed according to a zero-forcing algorithm, extended for a complex valued equalizer4. Instead of the multiplication necessary in the original algorithm, here the error signd

Passive CCD resonators [for high Q bandpass filters]

has to be multiplied only by the sign bit of thc estimated signal y. This can be realized simply by an EXOR-operation on the error word. The results of this operation are summed up in carry-save accumulator. The contents of the accumulators, as carryand sum words, arc sampled every 128 clock cycles, merged in a carry ripple adder and loaded onto the coefficient inputs of the filter. A shift register is used as a test-aid between the correlaY

A new SCCD specific measurement technique to determine the effective fast interface state density

The passive CCD resonator is a recursive CCD building block which is well suited for the realization of high Q bandpass filters. Its realization is compatible with the standard double-poly NMOS technology. Advantages of the new approach are an extremely low sensitivity of the center frequency which is determined by an external clock frequency, a relative bandwidth which does not depend on the center frequency but is controlled by a capacitance ratio, and signal frequencies at least up to some hundred kHz. The analysis, design considerations, and performance results are presented. A loaded Q factor of 30, a maximum stopband attenuation of 26 dB, and a negligible insertion loss in the passband are typical for a single CCD resonator. The maximum overall center frequency deviation /spl Delta/f/f due to fabrication tolerances is proportional to the transfer inefficiency of the CCD and has the value of about 2/spl times/10/SUP -4/.

Spectral density of noise in CCDs

Taking into account the thermally generated minority carriers to determine the background charge level along a SCCD, a measurement technique is described to obtain an effective fast interface state density N/SUB SSeff/. Compared to other SCCD specific methods the authors achieve better accuracy. The measurement technique is simple to apply and is useful to determine very small values of N/SUB SSeff/.

A CCD wave filter with low sensitivity

Good agreement between theory and measurements is obtained for the spectral density of transfer noise which is the dominant noise source in a SCCD. Within a frequencyband small compared to the baseband of the CCD the achievable signal-to-noise ratio S/N is limited by the noise power in that small frequency range and not by the mean square value. Our considerations show that the spectral density of noise power of a CCD is inverse proportional to the clock frequency fC. Therefore increasing fCimproves the S/N-ratio and enhances the performance of the CCD in band-limited analog communication systems.

Integrator with sampling stage

Starting with a double terminated Chebyshev LC ladder filter, a CCD wave filter has been implemented by using CCD resonators and charge amplifiers as basic building blocks. The bandpass filter which was realized on a test chip has a center frequency of 50 kHz, together with a relative Chebyshev bandwidth of 2.6 percent, 5 dB insertion loss, and more than 60 dB stopband attenuation. Compared to known SC filters, the advantages of the new approach are in extremely low sensitivity of the center frequency which is controlled by an external clock frequency, and a relative bandwidth which does not depend on the center frequency, but is controlled by capacitance ratios. Filter design, some aspects related to implementation, and experimental results are described.