Tobias Noll

Carry-save architectures for high-speed digital signal processing

Carry-save arithmetic, well known from multiplier architectures, can be used for the efficient CMOS implementation of a much wider variety of algorithms for high-speed digital signal processing than, only multiplication. Existing architectural strategies and circuit concepts for the realization of inner-product based and recursive algorithms are recalled. The twos complement overflow behavior of carry-save arithmetic is analyzed and efficient overflow correction schemes are given. Efficient approaches are presented for the carry-save, implementation of a saturation control. The concepts are extended and refined for the high-throughput implementation of decisiondirected algorithms such as division, modulo multiplication and CORDIC which have yet been avoided because of a lack of efficient concepts for implementation.It is shown, that the carry-save technique can be extended to a comprehensive method to implement high-speed DSP algorithms. Successfully fabricated commercial VLSI circuits emphasize the potential of this method.

Carry-save arithmetic for high-speed digital signal processing

It is shown that carry-save arithmetic, well known from multiplier architectures, can be used for the efficient CMOS implementation of a wide variety of algorithms for high-speed digital signal processing. Existing strategies for the realization of inner-product based and recursive algorithms are recalled. New approaches are presented for carry-save implementation of decision-directed algorithms such as division, modulo multiplication, and CORDIC.<<ETX>>

Pushing the performance limits due to power dissipation of future ULSI chips

The trend of power dissipation in current and future commercial CMOS integrated circuits is investigated considering that the minimum device size may scale down to about 0.1 mu m in the next decade. The power dissipation trend makes clear that it will be necessary to come up with some new concepts to reduce the power dissipation of future chips by an order of magnitude. The possibilities for doing this are analyzed on the architectural, logical, and layout level of the implementation. It is shown that pipelining is an attractive way of parallelization enforcing localization and short critical paths which are necessary to keep the power dissipation low. Approaches to reduce the power dissipation of the clock system in high-performance chips are discussed.<<ETX>>

A 2/spl mu/m Cmos Digital Adaptive Equalizer Chip For QAM Digital Radio Modems

IN HIGH-CAPACITY DIGITAL RADIO MODEMS employing multilevel quadrature modulation, adaptive time-domain equalizers are implemented to obtain the desired transmission performance. Toda , such equalizers are based on time-continous analog realizations , Fully digital implementation offers a number of important advantages such as stable and repeatable performance and lower cost, but challenges chip architecture and circuit technique to achieve the required data rate and computational complexity. In this paper the design and fabrication of a digital adaptive equalizer chip in CMOS technology will be described. Four of these chips have been used to implement a complex valued equalizer for QAM systems. The use of bit-level semi-systolic arrays as building blocks allows an effective implementation of the high speed portions of the chip. Because the chip set has to communicate with ECL chips (A/D converter and descrambler) and achieve low-power consumption, the inputs and outputs must be ECL-compatible. Synchronization on the between chips having different technology parameters, is a challenging condition, because worst case chips have t o communicate with best case chips. As shown in the block diagram of Figure 1, the digital adaptive equalizer chip contains a programmable nine-tap transversal filter, nine correlators, a cross channel adder (E), a programmable delay line (D) and a control logic block. The architecture of the transversal filter has been described*’ ’. This architecture, based on carry-save arithmetic, allows a small chip area and a high throughput rate independent of parameters like number of taps or wordlengths. In the correlators, the updating of coefficients is performed according to a zero-forcing algorithm, extended for a complex valued equalizer4. Instead of the multiplication necessary in the original algorithm, here the error signd

Wave digital filters using carry-save arithmetic

has to be multiplied only by the sign bit of thc estimated signal y. This can be realized simply by an EXOR-operation on the error word. The results of this operation are summed up in carry-save accumulator. The contents of the accumulators, as carryand sum words, arc sampled every 128 clock cycles, merged in a carry ripple adder and loaded onto the coefficient inputs of the filter. A shift register is used as a test-aid between the correlaY

CMOS digital adaptive decision feedback equalizer chip for multilevel QAM digital radio modems

A carry-save approach for the implementation of high-speed bit-parallel recursive digital filters is presented. Special mapping rules for translating a carry-propagate arithmetic into a carry-save arithmetic are described and finite wordlength effects, especially carry-save saturation characteristics and the truncation behavior, are considered to ensure the stability of the filters. The proposed carry-save arithmetics ensure the full pseudopassivity and the forced response stability of the circuits. The carry-save technique is illustrated with an example of a third-order lattice wave digital filter.<<ETX>>

Design and verification of a digital adaptive equalizer ASIC

The design of a complex-valued single-chip digital adaptive decision feedback equalizer for 256 quadrature amplitude modulation (QAM) radio modems is described. The chip contains 62000 transistors on a silicon area of 75 mm/sup 2/ and is designed for operation at frequencies of up to 70 MHz, in a 1.5- mu m CMOS technology. In high-speed applications clocking is a very critical issue in the systems design. The high operating frequency is achieved by performing a proper nonuniform redistribution of the delays over the data paths. The limitations are discussed for such a nonuniform distribution with respect to a maximum operating frequency required to be independent of the clocking scheme (i.e. nonoverlap of complementary two-phase clock system, etc.).<<ETX>>

Viterbi decoder for microwave digital radio-a novel architecture and system simulation results

The author describes the design and verification of a VLSI circuit which can be used to build up a complex-valued equalizer for digital radio modems operating at a symbol rate of typically 23.5 Mbd. Fabricated in a 2- mu m CMOS technology, the chip contains about 108000 transistors on a silicon area of 95 mm/sup 2/ and operates at a clock frequency of at least 23.5 MHz. The basic idea behind tackling the design complexity is to use regular, parameterizable, and optimized semisystolic macros as building blocks. It is shown that the applied design style allows a high level of design certainty and can ease the verification.<<ETX>>

A 4OMHz programmable semi-systolic transversal fitter

The performance of a Viterbi decoder in a microwave digital radio system with trellis-coded modulation is analyzed. As a result, signature curves are presented which show the performance of the Viterbi decoder on channels with intersymbol interference (ISI). As the best signature curves can be obtained using interleaving, an architecture for a VLSI Viterbi decoder chip based on this interleaving is derived.<<ETX>>

Connection and build-up technique for multichip modules

This paper will report on a transversal filter architecture with programmable coefficients. A test chip of a 7 tap fitter with 10b data, 8b coefficients and a 40MHz sampling rate has been realized. The 38.5K transistors with a total chip area of 14.6mm2in a 1.5μ CMOS technology achieve a functional throughput rate-per chip area of4×10^{12}Hz times gates per cm2.