Heinz Siegwart

Direct observation of the alignment of ferromagnetic spins by antiferromagnetic spins

The arrangement of spins at interfaces in a layered magnetic material often has an important effect on the properties of the material. One example of this is the directional coupling between the spins in an antiferromagnet and those in an adjacent ferromagnet, an effect first discovered in 1956 and referred to as exchange bias. Because of its technological importance for the development of advanced devices such as magnetic read heads and magnetic memory cells, this phenomenon has received much attention. Despite extensive studies, however, exchange bias is still poorly understood, largely due to the lack of techniques capable of providing detailed information about the arrangement of magnetic moments near interfaces. Here we present polarization-dependent X-ray magnetic dichroism spectro-microscopy that reveals the micromagnetic structure on both sides of a ferromagnetic–antiferromagnetic interface. Images of thin ferromagnetic Co films grown on antiferromagnetic LaFeO3 show a direct link between the arrangement of spins in each material. Remanent hysteresis loops, recorded for individual ferromagnetic domains, show a local exchange bias. Our results imply that the alignment of the ferromagnetic spins is determined, domain by domain, by the spin directions in the underlying antiferromagnetic layer.

Field-effect transistors with SrHfO3 as gate oxide

The authors demonstrate that the compound SrHfO3 grown epitaxially on Si(100) by molecular-beam epitaxy is a potential gate dielectric to fabricate n- and p-metal-oxide semiconductor field-effect transistors with equivalent oxide thickness (EOT) below 1nm. The electrical properties on capacitors and transistors show low gate leakage and good capacitance and I-V output characteristics. The lower electron and hole mobilities, which are strongly limited by charge trapping, nevertheless fit well with the general trend of channel mobility reduction with decreasing EOT.

Interface formation and defect structures in epitaxial La2Zr2O7 thin films on (111) Si

We have studied the growth of epitaxial La2Zr2O7 thin films on (111) Si. Although the interface structure can be strongly affected by the Si oxidation during the deposition process, epitaxial growth of La2Zr2O7 was obtained. A detailed study by means of transmission electron microscopy reveals two types of structures (pyrochlore and fluorite) with the same average chemical composition but strong differences in reactivity and interface formation. The structural complexity of the ordered pyrochlore structure seems to prevent excess oxygen diffusion and interfacial SiO2 formation.

Optical properties of epitaxial SrHfO3 thin films grown on Si

The perovskite SrHfO3 can be a potential candidate among the high-permittivity materials for gate oxide replacement in future metal-oxide semiconductor field-effect transistor technology. Thin films of SrHfO3 were grown by molecular beam epitaxy and compared with SrTiO3 films. Their optical properties were investigated using spectroscopic ellipsometry and analyzed with respect to their structural properties characterized by x-ray diffractometry, atomic force microscopy, and transmission electron microscopy. A band gap of Eg=6.1±0.1eV is measured optically, which renders this material better suited for gate dielectric applications than SrTiO3 with Eg∼3.4eV. At similar equivalent oxide thickness, SrHfO3 also exhibits lower gate leakage current than SrTiO3 does.

An integration path for gate-first UTB III-V-on-insulator MOSFETs with silicon, using direct wafer bonding and donor wafer recycling

In this work we demonstrate for the first time that the excellent thermal stability of ultra-thin body (UTB) III-V heterostructures on silicon provides a path for the cointegration of self-aligned In0.53Ga0.47As MOSFETs with silicon. We first demonstrate that the transfer of high-quality InGaAs / InAlAs heterostructures (tch <; 10 nm) can be achieved by direct wafer bonding and hydrogen-induced thermal splitting, and that the donor wafer can be recycled for a cost-effective process. The thermal stability of the bonded layer enables to integrate UTB III-V MOSFETs at 500 nm pitch using a gate-first flow featuring raised source/drain (S/D) grown at 600oC. The expected benefit of an UTB structure is benchmarked by comparing sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL) against state-of-the-art III-V-o-I or Tri-Gate FET data.

Solid phase epitaxy of SrTiO3 on (Ba,Sr)O∕Si(100): The relationship between oxygen stoichiometry and interface stability

Key aspects of the growth process of epitaxial SrTiO3 with crystalline interface on silicon are outlined. An important step in this process is the solid phase epitaxy in ultrahigh vacuum of amorphous SrTiO3 on top of a few monolayer thick, low-temperature grown, epitaxial (Ba,Sr)O∕Si(100) template. Insufficient oxygen supply during the SrTiO3 deposition step causes the formation of amorphous alkaline-earth silicates and TiSix at the Si∕epitaxial oxide interface during ultrahigh vacuum annealing. Performing SrTiO3 deposition in excess O2, this interfacial reaction is suppressed, and a metal-insulator-semiconductor capacitance equivalent to 0.5nm of SiO2 is obtained for a 10unit cell SrTiO3∕1unit cell (Ba,Sr)O∕p‐Si(100) stack.

Thermal stability of the SrTiO3∕(Ba,Sr)O stacks epitaxially grown on Si

The growth of epitaxial SrTiO3 on silicon relies on the preparation of a template layer consisting of a mixture of barium oxide and strontium oxide, (Ba,Sr)O. In this letter, the limited thermal stability of this template layer is demonstrated. X-ray photoemission spectroscopy measurements reveal that both SrTiO3∕(Ba,Sr)O and (Ba,Sr)O∕Si interfaces are susceptible to chemical reactions upon thermal treatment to an extent that is correlated with the thermal budget. These results have strong implications on the overall viability of (Ba,Sr)O as template for the growth of crystalline oxides on Si.

Phase of reflection high-energy electron diffraction oscillations during (Ba,Sr)O epitaxy on Si(100): A marker of Sr barrier integrity

We use the reflection high-energy electron diffraction oscillation phase shift to monitor the stability of the Sr barrier, prepared by exposure of Si(100) to Sr at high temperatures, in situ during molecular beam epitaxy growth of (Ba,Sr)O on Si(100). Our results confirm that the deposition of additional metallic Sr at low temperature is essential for preventing the incorporation of the Sr termination layer in the (Ba,Sr)O layer during its growth, and for obtaining monolayer thin (Ba,Sr)O layers with good crystallinity and minimal density of interfacial Si–O bonds on Si(100).

An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate (RMG) and Gate-first (GF) FETs are reported for the first time using InGaAs-OI wafers with a 120nm contact-to-contact pitch. Record ION (118 μA/μm) at fixed operating voltage of 0.5V for InGaAs devices on Si is achieved on 50-nm-Lg RMG FinFETs. Both schemes feature highly scaled fins (down to 15 nm). Compared to a GF integration flow, RMG devices exhibit better Ion and DIBL characteristics. We also demonstrate FETs with 70 nm contacts and 120 nm pitch achieving high-ION.

Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2 nm HfO2/1 nm Al2O3/1 nm a-Si gate stacks on p-In0.53Ga0.47As/InP (001) substrates. Thanks to the presence of the Al2O3 barrier layer, a minimum amount of the a-Si passivating layer is oxidized during the whole fabrication process. The capacitors exhibit excellent electrical characteristics with scaled equivalent oxide thickness (EOT) of 0.89 nm and mid-gap interface state density of 5 × 1011 eV−1 cm−2 upon post-metallization anneal up to 550 °C. Gate-first, self-aligned MOS field-effect-transistors were fabricated with a similar 5 nm HfO2/1 nm Al2O3/1 nm a-Si gate stack and raised source and drain (600 °C for 30 min). Owing to the excellent thermal stability of the stack, no degradation of the gate stack/semiconductor interface is observed, as demonstrated by the excellent capacitance vs voltage characteristics and the good mobility values (peak at 1030 cm2 V−1 s−1 and 740 cm2 V−1 s−1 at carrier density of 6.5 × 1012 cm−2...