Heinz Wohlrabe

Optimization of quality costs

Abstract The main goals of quality management in all industries are customer satisfaction by delivery of defect-free products and the radical reduction of defect rates and quality costs in the production. Controlled technological processes are the most important way to reach these goals. These principles are standard in mechanical engineering and are in use with great success. The properties in electronics production are different from the properties in mechanical engineering. During the assembly of electronic devices, processes are sensitive to the influences (environmental, parameter variation, etc.), that act on these processes. These influences are very strong, especially in the production of small batches of assemblies and a high mix of products. Processes can become uncontrolled, the defect rates can rise, and it is necessary to have inspection and repair processes after the different technological processes. But what about the quality costs? Is it sensible to do these quality control steps from the economical point of view? What is the right inspection strategy—no inspection or 100% inspection or statistical process control? To answer these questions new simple and powerful quality cost models have been developed at the Electronics Technology Laboratory and are in use in electronic producing industries. The quality costs are the “measurement system” to compare different inspection strategies with each other. The costs are calculated by the use of mathematical models—the quality cost models. To analyze and optimize the quality processes of a complete production line we use the method “Dynamic Programming”, developed by the American scientist, Bellman in the early 1950s of the 20th century.

Optimization of SMT solder joint quality by variation of material and reflow parameters

It is the objective of all PCB manufacturers to assure that each and every PCB supplied to the customer meets the specified quality requirements. Quality can be subdivided into two essential factors: the actual function of the PCB, and its reliability. Whereas function can, as a rule, be tested, only indirect substantiation is possible for reliability. The descriptions included in the IPC 610 D [1] standard are especially helpful in this respect, which indicate, amongst other things, which peculiarities the respective characteristics must demonstrate relative to product classes 1 through 3 in order to assure high reliability. At the same time, the number of repairs should be minimized to the greatest extent possible.

Evaluation of the quality of SMDs according to vacuum vapour phase soldering

In this paper an investigation on vacuum vapour phase soldering processes is presented. The purpose is to identify influencing factors of the solder profile with regard to the quality of the solder joint. For this the vacuum and the temperature profile were systematically varied and the void content, number of solder beads, wetting area and the number of tombstones were measured. An experimental board was designed to represent the effect on chip components, chip carrier and bare die packages in different sizes of each solder profile. Height measurement and X-Ray inspection were applied to gain information about the stand-off and void content. The vacuum pressure and the timing of the pressure variation were found to be the main influencing parameters.

R1 — A reliability comparison study between 14 lead free alloys

The reliability of solder joints is one important part of the quality of SMT-Boards. The paper presents a reliability study named R1. The base of the study is a reliability experiment with 14 different solder alloys (13 lead free solders and a Sn63 alloy as a reference), six different surfaces, six different SMD-chips combined with three different pad layouts. A high cycle reliability test was used. The times of failures were evaluated with the Weibull analysis followed by an analysis of variance.

Data mining in electronics packaging

In this paper the most common methods of data mining have been investigated and their application in electronics will be reflected. The current developments are systematized by the type of the used techniques. Therefore, a comprehensive literature review of data mining in electronics has been accomplished. The paper describes the usage of data mining in defect cause analysis, effects of process parameter for quality, deployment of equipment and maintenance. Examples of data mining applications in the literature have been summarized. A comprehensive experimental setup was the basis for the investigation on the effects on void generation. Statistical analysis and data mining techniques were used to identify the main causes for voids. The data file encompasses materials, suppliers, process parameters and inspection results. For a detailed analysis the x-ray inspection data of voids has been clustered into groups according to the dedicated package type. Finally, a neural network approach is applied to the experimental data and the model results are discussed.

Machine and process capability coefficient of solder paste printers

For manufacturers of assembled boards seeking ISO 9000 certification, a number of requirements are placed on measurement instruments and tooling. This standard requires a system to document and maintain calibration and machine capabilities. One of these problems is the measurement of printing accuracies of solder paste printers. The paper presents: short theoretical overview of machine capabilities; methods of measurement of accuracies (x, y and rotation); recommendations for the calibration of printers; indications for the sources of inaccuracies; practical examples and results.

Evaluation of the effects of the layout design on the quality of surface mount boards

This paper presents part of the results obtained after conducting an experiment designed with the help of the Design of Experiments (DoE) method. The aim of this experiment is to evaluate the dependencies between the layout design and the production quality of surface mount (SMT) boards. A test board was specially designed to allow us to vary certain factors. The DoE method was used to plan the variation of these factors in order to see their influences on the responses. The responses analyzed until now are: number of tombstones, wetting area, stand-off and existence of solder balls. The test was performed with 108 boards, two stencils, three solder pastes and three thermal profiles. Preliminary results show very few tombstones and good wetting areas for all three solder pastes in case of convection reflow. The heights for all components were measured before and after soldering. The analysis of the values obtained for the same chip component reveals that the stand-off difference (as we defined it) has the smallest value when the pad width is smaller than standard. Thus, the influence of the layout design on the quality of SMT boards can be observed.

Reliability Qualification of Flexible Printed Circuits with Common and New Methods

The use of FFC and FPC will constantly increase in the next years. The development of competitive products can be improved on basis of these technologies. However, the advantages within the range reliability and costs could only be used considering a complete view of the entire process chain efficiency and trend-setting. The complete verification and validating of FFC and FPC require substantial time expenditures. The introduction of new and reliable constructional-technological solutions presently requires too much time. For this reason we gradually compile a concept for the creation of time-efficient testing methods for FFC and FPC of products. We select substrate materials and connecting technologies with the necessary additive materials on the basis of well-known criteria. Duro plastic and thermoplastic materials can be used as substrate materials. In the initial phase we raise data from the results of the standardized accelerated aging procedures. Thus we use thermal test procedures and temperature storage with humidity. We characterize the test structures with destructive and non-destructive examinations. In the following stage we observe test superstructures under self-heating. We characterize the behavior of the test structures again with the well-known procedures. Additionally we measure the length variations in the total structure, brought in by the self-heating. The purposeful overlay and combination of different mechanical, thermal and chemical stresses to the total structure can substantially reduce the test phase in the future. In addition we are continuously acquiring data during the present phase. We designed a structure of test equipment, enabling these measurements. At the end of the running investigations at present we have data to plan the next stage with combined and selected aging procedures

Process and material effects on BGA board level solder joint reliability

This paper investigates the material, process and design influences on the reliability of BGA solder joints. The used methodology is a design of experiments. Factors are pad finish, type of solder paste, peak temperature, storage condition, the number of soldering cycles, the applied solder volume, and the land pad diameter. The reliability criterion is the number of failures after a thermo cycle test has been applied (5000TC). Failures have been detected using an electrical online measurements system. The effects on several process quality control variables and the target variable was evaluated. Results show that design parameters of the PCB affect the reliability significantly. Also material decisions have an impact on reliability. However, the assessed process variables do not show significant influences on reliability.

Changes of the coplanarity of SMT-components during soldering and their Measurement

The coplanarity between the substrate (or printed board) and the SMD-package is a very important characteristic. This coplanarity depends on the warpage of the board and the package. An insufficient coplanarity can lead to open solder joints and/or bridges of the solder joints. Additional mechanical stress (especially in z-direction) inside of the solder joints may also occur. The warpages of the packages and the boards change during a soldering process. The Thermoire®-Measurement gives the possibility to control the warpage under soldering conditions. The IPC-Bow and the IPC -Twist are characteristics, to evaluate the warpage of printed boards.