Henrik T. Jensen

Delta-Sigma modulator based A/D conversion without oversampling

Although /spl Delta//spl Sigma/ modulators are widely used for low to moderate rate analog-to-digital conversion, the time oversampling requirement has discouraged their application to higher rate converters. This paper presents an architecture wherein multiple /spl Delta//spl Sigma/ modulators are combined so that neither time oversampling nor time interlacing are necessary. Instead, the system achieves the effect of oversampling from the multiplicity of modulators. For a system containing M P/sup th/-order /spl Delta//spl Sigma/ modulators, approximately P bits of accuracy are gained for every doubling of M. A major benefit of the architecture is that it retains much of the robustness of the individual /spl Delta//spl Sigma/ modulators to nonideal circuit behavior. As a result, the architecture offers the potential of integrating high-precision, high-speed A/D converters together with digital signal processing functions using VLSI processes optimized for digital circuitry. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.

Oversampling parallel delta-sigma modulator A/D conversion

Conventional delta-sigma analog-to-digital converters (/spl Delta//spl Sigma/ADCs) are widely used in low-bandwidth applications such as high-fidelity audio processing because they offer high-precision conversion yet are amenable to implementation using fine-line VLSI processes optimized for digital circuitry. However, their oversampling requirement so far has prevented their widespread application to higher bandwidth applications such as video processing. This paper extends a recently developed delta-sigma ADC architecture called the pi-delta-sigma ADC (/spl Pi//spl Delta//spl Sigma/ADC) that consists of multiple /spl Delta//spl Sigma/ modulator channels operating in parallel without time-interleaving. The extension developed in this paper allows for oversampling to be combined with parallelism such that an M-channel system with an oversampling ratio of N can achieve a conversion performance close to that of a conventional /spl Delta//spl Sigma/ADC with an oversampling ratio of M/spl times/N. Thus, for a given conversion precision, the architecture offers relaxed oversampling relative to conventional /spl Delta//spl Sigma/ADCs in return for increased analog circuit area. Moreover, as will be shown, the /spl Pi//spl Delta//spl Sigma/ADC retains much of the robustness of conventional /spl Delta//spl Sigma/ADCs with respect to nonideal circuit behavior.

A low-complexity dynamic element matching DAC for direct digital synthesis

This paper presents and analyzes a new dynamic element matching technique for low-harmonic distortion digital-to-analog conversion. The benefit of this technique over the prior art is a significantly reduced hardware complexity with no reduction in performance. It is particularly appropriate for applications such as direct digital synthesis (DDS) in wireless communications systems, where low hardware complexity and low harmonic distortion are essential.

A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR

This paper presents a second-order /spl Delta//spl Sigma/ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-/spl mu/m, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the art performance in CMOS technology optimized for digital circuits.

A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs

A dynamic element matching (DEM) technique to mitigate the distortion caused by comparator offsets in the flash ADC of a /spl Delta//spl Sigma/ modulator is presented. Measurement results for a high-performance /spl Delta//spl Sigma/ modulator IC using comparator offset DEM are shown to demonstrate the significant reduction in offset-related spurious tones the technique provides. Analysis and simulation of comparator offset DEM in a flash ADC with a periodic input and uniform dither are presented to give insight into its operation and to quantify the spur attenuation it provides.

A reduced-complexity mismatch-shaping DAC for delta-sigma data converters

Although mismatch-shaping multi-bit DACs offer many advantages over single-bit DACs in delta-sigma data converters, most of the presently known mismatch-shaping DAC architectures involve a large amount of digital processing. This paper presents digital structures that implement previously published tree-structured mismatch-shaping DAC algorithms yet offer significant reductions in the digital processing.

An analysis of the partial randomization dynamic element matching technique

Partial randomization dynamic element matching (DEM) was recently introduced as a promising DEM technique for low harmonic distortion digital-to-analog conversion. The DEM technique is well suited to applications such as direct digital synthesis in wireless communication systems for which low hardware complexity is essential in addition to low harmonic distortion. Previously reported simulation results demonstrate that partial randomization DEM greatly attenuates harmonic distortion resulting from static errors in the analog output levels of the DAC, while offering considerable savings in hardware compared to other DEM techniques. This paper presents the first quantitative performance analysis of partial randomization DEM. As a main result, the minimum spurious-free dynamic range provided by the digital-to-analog converter has been quantified as a function of its hardware complexity and the analog output level errors.

A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD

This paper presents a second-order /spl Delta//spl Sigma/ modulator for audio-band A/D conversion implemented in a 3.3 V, 0.5 /spl mu/m, single-poly CMOS process that achieves 98 dB peak SINAD and over 100 dB SFDR. The design uses a reduced-complexity, mismatch-shaping 33-level DAC and a 33-level flash ADC with digital common-mode rejection and dynamic element matching of comparator offsets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS optimized for digital circuits. To the knowledge of the authors, this level of performance has not been achieved previously under these process constraints.

Clock distribution using coupled oscillators

This paper presents a robust, low complexity clock distribution technique applicable to both printed circuit boards and integrated circuits. The technique exploits the natural tendency of certain oscillators to lock in frequency and nearly lock in phase when coupled together. Experimental and theoretical results are presented that indicate the technique has the potential to dramatically reduce clock skew in digital circuits. A clock distribution architecture using the technique is proposed.

An area-efficient differential input ADC with digital common mode rejection

This paper presents a differential input flash ADC with digital common mode rejection (DCMR) and dithered, noise shaped requantization used in a high-performance, single-poly CMOS ADC /spl Delta//spl Sigma/ modulator IC. By avoiding the use of metal-metal capacitors, the DCMR flash ADC required 14% less area than a switched-capacitor implementation and avoided circuit implementation problems. Measurements and analysis show that the DCMR flash ADC rejects common mode noise without generating spurious tones. In the absence of common mode noise, its quantization noise power is equivalent to a conventional flash ADC.