Ian Galton

Spectral shaping of circuit errors in digital-to-analog converters

Recently, various multibit noise-shaping digital-to-analog converters (DACs) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DACs have the potential to significantly increase the present precision limits of /spl Delta//spl Sigma/ data converters by eliminating the need for one-bit quantization in delta-sigma modulators. This paper extends the practicality of the noise-shaping DAC approach by presenting a general noise-shaping DAC architecture along with two special-case configurations that achieve first- and second-order noise-shaping, respectively. The second-order DAC configuration, in particular, is the least complex of those currently known to the author. Additionally, the paper provides a rigorous explanation of the apparent paradox of how the DAC noise can be spectrally shaped even though the sources of the DAC noise-the errors introduced by the analog circuitry-are not known to the noise-shaping algorithm.

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.

Digital cancellation of D/A converter noise in pipelined A/D converters

Pipelined analog-to-digital converters (ADCs) tend to be sensitive to component mismatches in their internal digital-to-analog converters (DACs), The component mismatches give rise to error, referred to as DAC noise, which is not attenuated or cancelled along the pipeline as are other types of noise. This paper describes an all-digital technique that significantly mitigates this problem. The technique continuously measures and cancels the portion of the ADC error arising from DAC noise during normal operation of the ADC, so no special calibration signal or auto-calibration phase is required. The details of the technique are described in the context of a nominal 14-bit pipelined ADC example at both the signal processing and register transfer levels. Through this example, the paper demonstrates that in the presence of realistic component matching limitations the technique can improve the overall ADC accuracy by several bits with only moderate digital hardware complexity.

Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL

This paper describes a fractional-N PLL IC based on a new digital quantizer that replaces the DeltaSigma modulator (DeltaSigmaM) used in conventional designs. In combination with a charge pump offset technique and a sampled loop filter the new quantizer enables state-of-the-art fractional spur performance without sacrificing BW.

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma modulators, it does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a low-jitter clock. Therefore, it uses less area than comparable conventional delta-sigma modulators, and the architecture is well-suited to IC processes optimized for fast digital circuitry. The prototype IC is implemented in 65 nm LP CMOS technology with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8-17 mW, 0.5-1.15 GHz, 3.9-18 MHz, and 67-78 dB, respectively, and an active area of 0.07.

Delta-sigma data conversion in wireless transceivers

High-performance analog-to-digital converters, digital-to-analog converters, and fractional-N frequency synthesizers based on delta-sigma (/spl utri//spl Sigma/) modulation - collectively referred to as /spl utri//spl Sigma/ data converters have contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on /spl utri//spl Sigma/ data converters and their uses and implications with respect to wireless transceiver architectures.

A multiple-crystal interface PLL with VCO realignment to reduce phase noise

A phase realignment technique is applied to a ring oscillator VCO in a 3 V 6.8 mW CMOS PLL that converts most of the popular crystal reference frequencies to a 32 MHz baseband clock and RF PLL reference. The peak in-band phase noise at 20 kHz offset is -102 dBc/Hz with the technique enabled, and -92 dBc/Hz with the technique disabled.

Delta-Sigma modulator based A/D conversion without oversampling

Although /spl Delta//spl Sigma/ modulators are widely used for low to moderate rate analog-to-digital conversion, the time oversampling requirement has discouraged their application to higher rate converters. This paper presents an architecture wherein multiple /spl Delta//spl Sigma/ modulators are combined so that neither time oversampling nor time interlacing are necessary. Instead, the system achieves the effect of oversampling from the multiplicity of modulators. For a system containing M P/sup th/-order /spl Delta//spl Sigma/ modulators, approximately P bits of accuracy are gained for every doubling of M. A major benefit of the architecture is that it retains much of the robustness of the individual /spl Delta//spl Sigma/ modulators to nonideal circuit behavior. As a result, the architecture offers the potential of integrating high-precision, high-speed A/D converters together with digital signal processing functions using VLSI processes optimized for digital circuitry. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.

A Wide-Bandwidth 2.4 GHz ISM Band Fractional-

A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mus . The IC is implemented in 0.18 CMOS technology. It measures 2.2 x 22 mm2 and its core circuitry consumes 20.9 mA from a 1.8 V supply.