Herb Schwetman

Computer Systems Based on Silicon Photonic Interconnects

We present a computing microsystem that uniquely leverages the bandwidth, density, and latency advantages of silicon photonic interconnect to enable highly compact supercomputer-scale systems. We describe and justify single-node and multinode systems interconnected with wavelength-routed optical links, quantify their benefits vis-a-vis electrically connected systems, analyze the constituent optical component and system requirements, and provide an overview of the critical technologies needed to fulfill this system vision. This vision calls for more than a hundredfold reduction in energy to communicate an optical bit of information. We explore the power dissipation of a photonic link, suggest a roadmap to lower the energy-per-bit of silicon photonic interconnects, and identify the challenges that will be faced by device and circuit designers towards this goal.

Progress in Low-Power Switched Optical Interconnects

Optical links have successfully displaced electrical links when their aggregated bandwidth-distance product exceeds ~100 Gb/s-m because their link energy per bit per unit distance is lower. Optical links will continue to be adopted at distances of 1 m and below if link power falls below 1 pJ/bit/m. Providing optical links directly to a switching/routing chip can significantly improve the switched energy/bit. We present an early experimental switched CMOS-vertical-cavity surface-emitting laser (VCSEL) system operating at Gigabit Ethernet line rates that achieves a switched interconnect energy of less than 19 pJ/bit for a fully nonblocking network with 16 ports and an aggregate capacity of 20 Gb/s/port. The CMOS-VCSEL switch achieves an optical bandwidth density of 37 Gb/s/mm2 even when operating at a modest line rate of 1.25 Gb/s and is capable of scaling to much higher peak bandwidth densities (~350 Gb/s/mm2) with 5-10 pJ/switched bit. We also review a silicon photonic system design that will lower link energies to 300 fJ/bit, while providing multiterabits per second per square millimeter bandwidth densities. This system will ultimately provide switched optical interconnect at less than a picojoule per switched bit and computer/router system energies of tens of picojoule per bit. We review progress made to date on the silicon photonic components and analyze an energy and bandwidth-density roadmap for future advances toward these goals.

Silicon photonic WDM point-to-point network for multi-chip processor interconnects

We introduce a silicon photonic WDM point-to-point network enabled by novel optical proximity communications. This strictly non-blocking network provides scalable interconnectivity between chips low latency and high bisection bandwidth.

Wavelength stealing: an opportunistic approach to channel sharing in multi-chip photonic interconnects

Silicon photonic technology offers seamless integration of multiple chips with high bandwidth density and lower energy-per-bit consumption compared to electrical interconnects. The topology of a photonic interconnect impacts both its performance and laser power requirements. The point-to-point (P2P) topology offers arbitration-free connectivity with low energy-per-bit consumption, but suffers from low node-to-node bandwidth. Topologies with channel-sharing improve inter-node bandwidth but incur higher laser power consumption in addition to the performance costs associated with arbitration and contention. In this paper, we analytically demonstrate the limits of channel-sharing under a fixed laser power budget and quantify its maximum benefits with realistic device loss characteristics. Based on this analysis, we propose a novel photonic interconnect architecture that uses opportunistic channel-sharing. The network does not incur any arbitration overheads and guarantees fairness. We evaluate this interconnect architecture using detailed simulation in the context of a 64-node photonically interconnected message passing multichip system. We show that this new approach achieves up to 28% better energy-delay-product (EDP) compared to the P2P network for HPC applications. Furthermore, we show that when applied to a cluster partitioned into multiple virtual machines (VM), this interconnect provides a guaranteed 1.27× higher node-to-node bandwidth regardless of the traffic patterns within each VM.

Optical Interconnect for High-End Computer Systems

Advances in silicon photonic technology have made possible the use of optical communication in large-scale chip arrays. This article shows how such a structure utilizes the high bandwidth of the optical links through optical proximity communication that enables significant levels of device integration.

Energy-Efficient Error Control for Tightly Coupled Systems Using Silicon Photonic Interconnects

Future computer systems will require new levels of computing power and hence new levels of core and chip densities. Because of constraints on power and area, optical interconnection networks will play a critical role in these new systems. In this paper, we describe the macrochip, a multi-chip node with an embedded silicon photonic interconnection network that consists of thousands of optical links. For such a large-scale wavelength division multiplexing optical network, we show how to use an energy-efficient error control scheme employing variable-length cyclic redundancy check codes to achieve a desirable residual bit error rate (BER) of 10-23 for reliable system operation with the individual link BER at 10-12 or higher. We use a discrete-event network simulation of the macrochip using uniform random traffic to show that our scheme incurs minimal impact on performance compared to a perfect system with no error control. Using link level energy efficiency and network throughput analysis, we estimate and report network level energy efficiency using the metric of energy per useful bit.

Dense WDM silicon photonic interconnects for compact high-end computing systems

We present the design of a silicon microsystem that utilizes dense, low-power photonic interconnects to enable a highly-compact supercomputer-scale system. We review recent progress in wavelength-division multiplexed, low-power silicon photonic interconnect components and discuss a future roadmap for the technology.

Optical Interconnects in the Data Center

Optical interconnects in large-scale systems offer the possibility of new system topologies, with many multi-core processors and memories integrated together and densely co packaged. This opens up new possibilities in large-scale installations like data centers, supporting both commercial and scientific applications. A first step is to explore the optical and electrical circuits and devices required to create optical links, but many interesting research questions remain about how to construct large-scale systems that employ those links.

The integration of silicon photonics and VLSI electronics for computing systems

We review the potential benefits and challenges for achieving optical-interconnects to the chip via the native integration of silicon photonics components with VLSI electronics; and introduce the “macrochip” — a collection of contiguous silicon chips enabled by optical proximity communication.

An Energy-Efficient Optical Interconnect Architecture for Bandwidth-Balanced Systems

Systems comprised of interconnected computing nodes present a number of design challenges. In this paper, we present and, then, analyze a design for a power-efficient, bandwidth-balanced system to meet a performance goal of 1 PFlops. We show that the on-node bandwidth required to support internode communications grows as the data-locality of an application decreases. We present an internode network that reduces this on-node bandwidth requirement to meet the limitations of the system building block (the macrochip) and introduce a new silicon photonics-based switch called the macroswitch. Our analysis demonstrates that a bandwidth-balanced system based on the macroswitch and photonic interconnects can achieve the stated goals with significantly lower power than an evolutionary system based on conventional multilevel switches.