Jon Lexau

Two FIFO ring performance experiments

Asynchronous circuits are often perceived to operate slower than equivalent clocked circuits. We demonstrate with fabricated chips that asynchronous circuits can be every bit as fast as clocked circuits. We describe two high-speed first-in-first-out (FIFO) circuits that we used to compare the performance of asynchronous FIFOs with that of conventionally clocked shift registers. The first FIFO circuit uses a pulse-like protocol, which we call the Asynchronous Symmetric Persistent Pulse Protocol (asP*), to advance data along a pipeline of conventional latches. Use of this protocol requires careful management of circuit delays. The second FIFO circuit uses a transition signaling protocol and special transition latches to store data. These transition latches are fast, but they are about 50% larger than conventional latches. Measurements obtained from chips fabricated in 0.6 /spl mu/m CMOS and from SPICE simulations show that the throughput of the first FIFO design matches that of a conventionally clocked shift register design, with a maximum throughput of 1.1 Giga data items per second. The throughput of the second design exceeds the performance of the asP* design and achieves a maximum throughput of 1.7 Giga data items per second. We have extensively tested the chips and have found them to operate reliably over a very wide range of conditions.

High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS

Long on-chip wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, proliferating repeater farms add significant complexity to full-chip integration, motivating circuits to improve wire performance and energy while reducing the number of repeaters. Such methods include capacitive-mode signaling, which combines a capacitive driver with a capacitive load [1,2]; and current-mode signaling, which pairs a resistive driver with a resistive load [3,4]. While both can significantly improve wire performance, capacitive drivers offer added benefits of reduced voltage swing on the wire and intrinsic driver pre-emphasis. As wires scale, slow slew rates on highly resistive interconnects will still limit wire performance due to inter-symbol interference (ISI) [5]. Further improvements can come from equalization circuits on receivers [2] and transmitters [4] that trade off power for bandwidth. In this paper, we extend these ideas to a capacitively driven pulse-mode wire using a transmit-side adaptive FIR filter and a clockless receiver, and show bandwidth densities of 2.2–4.4 Gb/s/µm over 90nm 5mm links, with corresponding energies of 0.24–0.34 pJ/bit on random data.

Ultralow-power silicon photonic interconnect for high-performance computing systems

The Ultra-performance Nanophotonic Intrachip Communication (UNIC) project aims to achieve unprecedented high-density, low-power, large-bandwidth, and low-latency optical interconnect for highly compact supercomputer systems. This project, which has started in 2008, sets extremely aggressive goals on power consumptions and footprints for optical devices and the integrated VLSI circuits. In this paper we will discuss our challenges and present some of our first-year achievements, including a 320 fJ/bit hybrid-bonded optical transmitter and a 690 fJ/bit hybrid-bonded optical receiver. The optical transmitter was made of a Si microring modulator flip-chip bonded to a 90nm CMOS driver with digital clocking. With only 1.6mW power consumption measured from the power supply voltages and currents, the transmitter exhibits a wide open eye with extinction ratio >7dB at 5Gb/s. The receiver was made of a Ge waveguide detector flip-chip bonded to a 90nm CMOS digitally clocked receiver circuit. With 3.45mW power consumption, the integrated receiver demonstrated -18.9dBm sensitivity at 5Gb/s for a BER of 10-12. In addition, we will discuss our Mux/Demux strategy and present our devices with small footprints and low tuning energy.

CMOS Integration of Capacitive, Optical, and Electrical Interconnects

We present a 90 nm test chip integrating proximity communication, optics using external lasers and photodiodes, and CML electronics on a single CMOS chip which can route data at multi-Gb/s rates through any combination of its three interconnect interfaces. A robust and flexible unclocked datapath allows independent timing and margin characterization of each path.

BGA package integration of electrical, optical, and capacitive interconnects

We present a novel optically-enabled ball grid array (OBGA) package that integrates conventional electrical I/O, proximity communication (PxC), and optical communication in one industry-compatible BGA package for the first time. The key enabling technologies for such a packaging solution, including the precision alignment needed to combine multiple CMOS chips and compact opto-electronic (OE) subassemblies, are detailed here. We designed and fabricated a 45 mm × 45 mm × 5.2 mm organic cavity-down BGA package with up to 600 solder balls for electrical I/O. Its cavity holds three CMOS chips, with PxC interfaces and optical driver/receiver circuits, as well as two multi-channel optical subassemblies with standard optical fiber connections. We report preliminary testing results.

A silicon photonic WDM network for high-performance macrochip communications

We introduce a novel approach to interconnect multiple chips together with a silicon photonic WDM point-to-point network enabled by optical proximity communications to act as a single large piece of logical silicon much larger than a single reticle limit. We call this structure a macrochip. This non-blocking network provides all-to-all low-latency connectivity while maximizing bisection bandwidth, making it ideal for multi-core and multi-processor interconnections. We envision bisection bandwidth up to TBps for an 8x8 macrochip design. And a 5-6x improvement in latency can be achieved when compared to a purely electronic implementation. We also observe better overall performance over other optical network architectures.

Delivering On-chip Bandwidth Off-chip and Out-of-box with Proximity and Optical Communication

While copper-based electrical Serdes links have, to date, dominated the domain of ultra-short reach interconnects, future high-performance computers may require the integration of diverse interconnect technologies. In previous chapters, various forms of proximity communication that can provide low-energy chip-to-chip links between adjacent chips have been described. The strengths of proximity communication lie in low-energy short-distance links; the strengths of optical communication lie in efficiently reaching longer distances. Here we look to combine these technologies in a new hybrid I/O platform that can deliver balanced bandwidth on-chip, off the chip and even out of the box. In this chapter we will introduce the concepts of an optical-to-proximity interface chip, and review results from an experimental 90 nm test chip that integrates three types of high-speed chip-to-chip interconnects: capacitive interconnects for proximity communication; optical interconnects employing vertical-cavity surface-emitting lasers (VCSELs) and photodiodes; and electrical interconnects using current-mode logic (CML). We will discuss the operation and compatibility of each interconnect modality, and review interface requirements, chip layout considerations and test results.

Communication in macrochips using silicon photonics for high-performance and low-energy computing

There have been a number of recent high-profile advances in silicon-integrated optical devices, including low-loss silicon waveguides, integrated laser modulators and photodetectors, optical gratings for surface-normal attach of fibers to chips, and many more. These technologies open the possibility of using silicon-based nano-photonics inside a traditional computer system based on very large scale integration (VLSI) chips using todays most advanced complementary metal-oxide-silicon (CMOS) technologies. Such a system might offer the cost and computing performance advantages of modern microprocessors in conjunction with the low latency and enormous bandwidth of wavelength-division multiplexing (WDM) optics.