Herbert L. Ho

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm2 deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line. A dynamic-and-gate-thin-oxide word-line driver that tracks standard logic process variation improves the eDRAM array performance with reduced area. The 1.1 Mb macro composed of 8 ×2 72 Kb subarrays is organized with a center interface block architecture, allowing 1 ns access latency and 1 ns bank interleaving operation using two banks, each having 2 ns random access cycle. 5 GHz operation has been demonstrated in a system prototype, which includes 6 instances of 1.1 Mb eDRAM macros, integrated with an array-built-in-self-test engine, phase-locked loop (PLL), and word-line high and word-line low voltage generators. The advantage of the 14 nm FinFET array over the 22 nm array was confirmed using direct tester control of the 1.1 Mb eDRAM macros integrated in 16 Mb inline monitor.

In-line characterization of EDRAM for a FINFET technology using VC inspection

An E-beam voltage contrast inspection methodology involving multiple inspection points has been created to support development of the EDRAM module for a recent FINFET technology. This methodology provides within-sector feedback for a wide range of defect types enabling fast turn-around of split experiments and early detection of process excursions. Most defectivity affecting EDRAM is buried and therefore not detectable with broad beam plasma inspection. The EDRAM module is first in the process sequence for this FINFET technology. Without E-beam inspection, the first opportunity for defectivity feedback would be metal 1 test, which is months later in the process sequence. While direct E-beam inspection of functional EDRAM is a key part of this methodology, many defect types cannot be detected directly on functional SRAM. Special voltage contrast test structures were designed to monitor these defect types. The key defect types and the strategy used to detect each of them is described in detail in this paper. Select split experiment and process excursion data are used to illustrate the impact of the methodology.