Herman Jalli Ng

Scalable sensor platform with multi-purpose fully-differential 61 and 122 GHz transceivers for MIMO radar applications

This paper describes a scalable sensor platform consisting of several multi-purpose 61 and 122 GHz transceivers that are designed in a fully-differential architecture and implemented in a Silicon-Germanium BiCMOS technology. The former transceiver achieves a higher transmit output power as well as receive gain and is meant for applications requiring a high dynamic range, while the latter transceiver allows a higher modulation bandwidth and is meant for high resolution applications. The transceivers include a frequency multiplier that generates the 61 and 122 GHz carrier signals from a single external 30.5 GHz LO signal that is also fed to an output buffer in the transceivers. The proposed architecture enables the cascading of multiple transceivers and allows thus the implementation of a MIMO radar system with 2 different frequency bands. The transceivers are equipped with BPSK modulators as well as an I/Q receiver and can be utilized as a base to build a very flexible software-defined radar platform.

Industrial mmWave Radar Sensor in Embedded Wafer-Level BGA Packaging Technology

We present highly integrated 60-GHz radar transceivers for industrial sensor applications. The bistatic and monostatic transceivers are implemented in the SiGe bipolar technology and packaged using the embedded wafer-level ball grid array technology that allows for direct embedding of the antennas in the package redistribution layer. In this way, very compact and efficient radar frontends comprising all millimeterwave components can be implemented in an 8 × 8 mm2 package. These frontends were soldered on a standard low-cost printed circuit board based on FR4 material. For verification of the proposed frontends, an frequency-modulated continuous wave (FMCW) radar system was developed and set up within this paper. Theoretical considerations and simulations as well as corresponding measurements were carried out for the evaluation of the designed system. The demonstrator results of these embedded radar sensors show an excellent system performance at a high integration level.

Miniaturized 122 GHz system-on-chip radar sensor with on-chip antennas utilizing a novel antenna design approach

This paper describes a highly-integrated 122 GHz system-on-chip radar sensor in a SiGe BiCMOS technology. The chip includes a radar transceiver and two on-chip antennas utilizing a novel antenna design approach that allows the use of the localized backside etching technique without compromising the mechanical stability of the chip. The implemented double folded dipole antenna achieves an antenna gain of 6 dBi with a radiation efficiency of 54%. The transceiver is equipped with a 61 GHz VCO that is complemented with a frequency doubler to generate the transmit signal. The receive path includes an LNA, a 90 degree coupler, two passive subharmonic mixers and variable gain amplifiers. Radar measurements with static as well as moving targets were done to show the applicability of the developed system.

0.1mm 2 SiGe BiCMOS RX / TX channel front-ends for 120 GHz phased array radar systems

This paper presents both differential receiver and transmitter front-end modules for a 120 GHz phased array transceiver for the use in FMCW radar applications. A Gilbert-cell based vector modulator type I/Q phase shifter is accompanied by integrated LNA / PA in RX / TX channels fabricated with a 0.13µm SiGe BiCMOS technology with fT/fmax of 250/340GHz. Measurements show a 15 dB peak gain with 14 GHz bandwidth for the RX channel consuming 125mW from a 2.5V supply. Furthermore, the designed TX channel achieves a gain of 18 dB with 10.5 GHz bandwidth and an output referred 1dB compression point of 2.7 dBm with 6.4 dBm saturated output power at a power consumption of 225mW. These fully differential core frontends provide continuous 360° phase shift and only occupy an ultra-low area of 0.4mm × 0.25mm allowing a high degree of channel integration.

Design of a low-jitter wideband frequency synthesizer for 802.11ad wireless OFDM systems using a frequency sixtupler

The rms timing jitter of a phase-locked loop (PLL) is calculated and minimized analytically from the VCO phase noise and the in-band phase noise plateau with and without digital baseband correction in an OFDM system. Subsequently, we present an integrated wideband frequency synthesizer in a 130 nm SiGe BiCMOS technology. An 8.7GHz-11.8GHz PLL using only one VCO is followed by a frequency sixtupler composed of a tripler and a doubler. The measured phase noise at 1 MHz offset from the 10 GHz PLL output frequency is below −108 dBc/Hz. For a 60 GHz OFDM system, this corresponds to an rms phase error of 1.5° and a PLL rms jitter of 70 fs after common phase error correction. The synthesizer chip occupies a chip area of 3.6 mm2 and draws 144 mA from a 3.3 V supply.

Analysis of Ranging Precision in an FMCW Radar Measurement Using a Phase-Locked Loop

The standard deviation in a frequency modulated continuous wave radar distance measurement using a charge pump phase-locked loop (PLL) is calculated analytically. The phase noise of the PLL is modeled as an Ornstein–Uhlenbeck process resulting in a Lorentzian spectrum. We calculate the distance error as a function of the receiver noise bandwidth and the target distance. Depending on the frequency estimation algorithm and the target distance, the rms distance error due to PLL phase noise increases by about 6–9 dB with doubling the target distance. By contrast, the white noise in the radar receiver raises the distance error by about 12 dB in the far field with distance doubling, making this error contribution dominant for large target distances. These findings are verified by measurements on a scalable 61/122-GHz radar sensor platform.

An integrated 240 GHz differential frequency sixtupler in SiGe BiCMOS technology

An integrated frequency sixtupler in SiGe BiCMOS technology is presented. It is composed of a nonlinear differential amplifier used as a frequency tripler followed by a Gilbert mixer used as a frequency doubler. The 3 dB bandwidth of the circuit is 15GHz in between 222 – 237GHz range with peak output power of −4 dBm for 0dBm input power. The suppression of the 120GHz feed through signal at the mixer output is better than 14 dB while the 5th and the 7th harmonics are suppressed by more than 18 dB. The circuit consumes 900mW from a 4.7V supply. It is preceded by a differential amplifier functioning as an active balun to generate differential signals for the tripler.

Highly-miniaturized 2-channel mm-wave radar sensor with on-chip folded dipole antennas

This paper describes a miniaturized 2-channel system-on-chip radar sensor in a SiGe BiCMOS technology. It includes on-chip folded dipole antennas that utilize a localized backside etching technique with a novel selective etching approach that is able to improve the radiation efficiency and the mechanical stability of the chip. The transceiver is equipped with a 30-GHz VCO that is complemented with a frequency quadrupler to generate a 120-GHz carrier signal. The 2 transmit channels can be combined to increase the effective isotropic radiated power by 6 dB and to implement a SIMO radar. The transceiver also includes BPSK modulators as well as I/Q receivers and can be utilized to build a flexible MIMO radar using frequency-modulated continuous-wave with time and delta-sigma modulator-based frequency division multiplexing as well as pseudo-random noise radar techniques. Radar measurement using digital-beamforming method with 10-GHz modulation bandwidth was performed to show the applicabilty of the proposed system.

A low-power 190–255 GHz frequency quadrupler in SiGe BiCMOS technology for on-chip spectroscopic applications

This paper presents the design of a wide-band frequency quadrupler in the 240 GHz frequency regime fabricated in a 0.13 μm SiGe BiCMOS process. Frequency multiplication is performed in two stages: in the first stage, two push-push doublers with quadrature input double the input frequency and in the second stage, a bootstrapped Gilbert-cell doubler delivers quadrupled signal at the output. A Marchand balun and a polyphase filter (PPF) transform the single-ended input into a differential quadrature signal. The differential output has been converted into a single-ended signal using a rat-race coupler. The quadrupler shows a 3-dB bandwidth of 29.2 % (190–255 GHz) and the maximum output power is −16.4 dBm. The chip is 0.45 mm2 and consumes 48 mW power. As a wide-band quadrupler, this chip is a useful building block for on-chip low-power dielectric spectroscopy.

Scalable pseudo-random noise radar

This paper describes the implementation of a pseudo-random noise radar system on a scalable sensor platform that consists of several multi-purpose 61- and 122-GHz transceivers in a Silicon-Germanium BiCMOS technology. The multi-band transceivers are equipped with a frequency multiplier to generate the 61- and 122-GHz carrier signals from a single 30.5-GHz LO signal and can be cascaded to build a MIMO radar system with 2 different frequency bands. The implemented scalable sensor system is suitable for various radar and communication applications by using the same transceiver chips with integrated binary phase-shift keying modulators and I/Q receiver. A suitable pseudo-random binary sequence was used in a radar measurement to demonstrate the applicability of the developed chips.