Herman Norde

A modified forward I‐V plot for Schottky diodes with high series resistance

It is shown that by plotting the function F (V) =V/2−(kT/q)  ln(I/AA**T2) a reliable value of the barrier height can be obtained even if there is a series resistance which would hamper the evaluation of the standard lnI‐vs‐V plot. A theoretical examination of F (V) is followed by experimental plots for some common Schottky‐barrier diodes.

Complementary Si MESFET concept using silicon-on-sapphire technology

Complementary Si MESFETs (CMES) for integrated circuits using silicon-on-sapphire are described. Not only the gate, but also the source and drain of the n-transistors and p-transistors are Schottky junctions, using very high barrier heights for the gate and low barrier heights for source and drain. Only two Schottky metals are used: one, Ir or Pt, giving a high barrier on nSi, and hence low on pSi; the other, Er or Tb, showing the opposite behavior. The basic differences between MES and MOS are pointed out and design criteria for CMES inverters using normally-off type transistors are given.<<ETX>>

Schottky rectifiers on silicon using high barriers

Abstract Schottky diodes are presently used for power rectification because of their low forward voltage drop. However, they have only been fabricated on relatively low resistivity and thin semiconductor layers. Hence the reverse breakdown voltages are low. To make diodes that stand higher reverse voltages, low doped material of sufficient thickness is necessary. Ordinary Schottky barriers do not inject minority carriers and the resistive voltage drop at high forward currents will be large, However, for high Schottky barriers ∼ 0.9eV, minority carriers are injected and the series resistance is decreased. In this paper we report results from one-dimensional numerical calculations as well as experimental results of high barrier Schottky diodes. We discuss the voltage drop at high forward currents for different substrate resistivity and thickness, as well as values of the high barrier.

A capacitance-voltage measurement method for DMOS transistor channel length extraction

This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 /spl mu/m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.

Subthreshold behaviour of silicon MESFETs on SOS and bulk silicon substrates

Abstract The subthreshold characteristics of silicon MESFETs manufactured using both bulk silicon and silicon-on-sapphire (SOS) technology, have been studied. n - and p -type devices have been investigated and their characteristics are presented here. The results show that the subthreshold behaviour for bulk devices in fully comparable with that of MESFETs, while the SOS devices show a somewhat lower value of subthreshold swing. A comparison between calculated and experimental behaviour is presented which yields information about the influence of the geometry and processing parameters of the subthreshold behaviour. It is proposed that the saturation subthreshold current for bulk transistors can be decreased by a proper design. An improvement for SOS devices, however, requires improved substrate material.

Contact Resistance Measurements of Platinum-Silicide and Chromium Contacts to Highly Doped n and p Silicon

A comparison of contact resistivity for platinum silicide contacts and sputtered chromium contacts to heavily doped n and p silicon has been done, by a method which is suitable for contacts on a highly conductive surface layer on a less conductive base material. Good statistics was obtained by using 50 separate structures on each wafer. The results showed less spreading and lower specific contact resistance for PtSi contacts on both n+ and p+-Si, than for Cr contacts which on p+ showed a non-ohmic behaviour.

Computer modeling and comparison of different rectifier (M-S, M-S-M, p-n-n + ) diodes

A computer method is used to investigate the forward characteristics of high-barrier Schottky diodes with different back contacts. A discussion of rectifier-parameter optimization is presented, together with comparisons of different diode types, including p-n-n+diodes. The superiority, in certain voltage ranges, of the high-barrier Schottky diodes over p-n-n+diodes is demonstrated.

Barrier heights to silicon, of ruthenium and its silicide

The Schottky barrier height between as‐deposited, as well as heat‐treated samples of Ru metal deposited onto n‐type silicon was determined, using forward IV data and photoelectric response measurements. When no silicide formation was observed (using Rutherford backscattering analysis) a barrier height of φBo = 0.79±0.01 eV was found. Where heat treatment resulted in formation of RuSi1.5 (reported to be semiconducting), the barrier height varied in the range 0.70– 0.74 eV. We included recent barrier‐height data for the other 4d‐series elements with our results and found a trend of increase of barrier height with work function, similar to that found for the 5d series.

Parallell-Plate Electron Multipliers

A review is given of the properties of parallel plate electron multipliers and present development work is described. In particular the type of multiplier fabricated by RF-sputtering of separate potential divider and secondary emission layers is discussed. This allows optimization of the two functions. Typical plate dimensions are 2O×2O mm, with a separation of ? 0.3 mm. The theories for the straight pipe-shaped multiplier and the parallel plate multipliers are discussed and a comparison is made with measurements, The influence of the geometry is discussed, including optimum plate spacing. A difference compared with tubular multipliers is that electron avalanches spread sideways, because of statistics and electric repulsion effects. Studies of pulse shapes and timing properties are reported. Current pulses at the oultput are about 10 nsec long, for each electron avalanche, Severlal superimposed avalanches caused by ionic feedback build up the integrated voltage pulse to a length of a few tenths of a ?sec.

Junctions Between Amorphous and Crystalline Silicon

Amorphous/crystalline Si junctions were fabricated by sputter-deposition of amorphous Si from p- and n-type targets, onto p- and n-type monocrystalline silicon. The barrier heights were determined from I-V and C-V measurements for as-deposited, and for annealed junctions. The electron barriers were 0.32-0.35 eV and the hole barriers 0.74-0.86 eV, depending on treatment. Sputtering from p- or n-type targets was of minor importance, as well as moderate annealing (400°C, 1/2 hr). These properties are similar to those of amorphous Ge on crystalline silicon junctions.