U Magnusson

Complementary Si MESFET concept using silicon-on-sapphire technology

Complementary Si MESFETs (CMES) for integrated circuits using silicon-on-sapphire are described. Not only the gate, but also the source and drain of the n-transistors and p-transistors are Schottky junctions, using very high barrier heights for the gate and low barrier heights for source and drain. Only two Schottky metals are used: one, Ir or Pt, giving a high barrier on nSi, and hence low on pSi; the other, Er or Tb, showing the opposite behavior. The basic differences between MES and MOS are pointed out and design criteria for CMES inverters using normally-off type transistors are given.<<ETX>>

An improved silicon p-channel MESFET with a BF2 implanted thin channel and ErSi2 gate

Abstract To develop a process for making complementary silicon MESFETs it is of utmost importance to achieve high performance MESFETs. Especially the p -channel MESFETs need improvement of driving capability and switching speed. In this article, we will report results from a p -channel MESFET having an ErSi 2 gate, fabricated using bulk silicon technology. This device exhibits improved values of transconductances as compared to earlier fabricated devices. This is mainly due to the fabrication of a controlled thin channel, manufactured by the BF 2 implantation technique. Also, the subthreshold characteristics of this improved device is presented and is found to be comparable to MOS p -channel devices.

Subthreshold behaviour of silicon MESFETs on SOS and bulk silicon substrates

Abstract The subthreshold characteristics of silicon MESFETs manufactured using both bulk silicon and silicon-on-sapphire (SOS) technology, have been studied. n - and p -type devices have been investigated and their characteristics are presented here. The results show that the subthreshold behaviour for bulk devices in fully comparable with that of MESFETs, while the SOS devices show a somewhat lower value of subthreshold swing. A comparison between calculated and experimental behaviour is presented which yields information about the influence of the geometry and processing parameters of the subthreshold behaviour. It is proposed that the saturation subthreshold current for bulk transistors can be decreased by a proper design. An improvement for SOS devices, however, requires improved substrate material.

A Lateral Bipolar Transistor Concept on SOI using a Self-Aligned Base Definition Technique

A lateral bipolar transistor technology for the fabrication of high performance lateral devices on SOI is presented. The presented technology makes use of selective etching procedures and time controlled wet etching to define the basewidth of the devices. 2-D process simulation results are presented together with 2-D device simulations showing the applicability of the proposed process.

Investigation of the current-voltage behavior of a combined Schottky-p-n diode

Abstract An investigation of the current-voltage ( I - V ) behaviour of a mixed Schottky - p - n structure is presented. Designed in a proper way, this component will combine the low forward voltage drop of the Schottky diode and the high current properties of the p - n junction. In this article experimental I - V characteristics of a device manufactured using Ag diodes, integrated within a p - n diode structure, are presented. The characteristics show the expected similarity with Schottky barrier diodes for low forward voltages. It is shown that, even for high forward bias, for some Schottky- p - n area ratios the combined diode has higher current capability than a conventional p - n diode.

Investigations of evaporated silicon p-n junctions and their application to junction field-effect transistors

p‐n junctions formed by vacuum evaporation of silicon on crystalline silicon have been investigated. The junctions were formed by ion implantation of 49BF+2 in the evaporated silicon films. Subsequently, an isochronal heat treatment in the range of 600–850 °C was performed and its influence on the doping distributions and corresponding diode behavior was studied. Secondary‐ion mass spectrometry was used to investigate the resulting boron distributions. A sharp decrease in the boron concentration was found at the interface for the sample annealed at 850 °C.The fabricated p‐n junctions were evaluated by measuring the current‐voltage characteristics. Comparisons were made to ordinary diffused p‐n junctions in bulk silicon. Using the current‐voltage measurements, the leakage current and the ideality factor of the diodes were extracted. The reverse currents were also measured and show a nonsaturating behavior. The resistivity of the films were investigated as a function of anneal temperature, and it was found ...

Influence of silicon-sapphire interface defects on SOS MESFET behavior

Abstract Silicon MESFETs in silicon-on-sapphire SOS technology were studied and a comparison was made between simulated and measured I - V characteristics of normally-off transistors. The comparisons have shown that the effective conducting-channel depth is only 40% of the actual Si film thickness. A novel simulation approach to compensate for the lack of free carriers close to the sapphire interface is described. Results from measured transistors is presented together with simulated behavior, and also a comparison between simulated and experimental complementary MESFET (CMES) inverter behavior is done. The influence of interface defects on subthreshold current is also discussed.

Ultrashallow diffused n+p junction using antimony for device applications

Experimental characteristics of ultrashallow n+p junctions manufactured by vacuum evaporation of antimony (Sb) and silicon (Si), followed by heat treatments to recrystallize the amorphous silicon, are presented. It is found that the n+p junction is located less than 300 A inside the crystalline silicon and that all Sb is redistributed within the regrown film. Comparisons with Schottky (Sb‐Si) diodes show that with a heat treatment at 900 °C, the diodes convert fully from Schottky type to n+p type. Furthermore, normally off‐type junction field‐effect transistors have been fabricated using these n+p junctions as gate junctions, and the characteristics are presented together with data concerning threshold voltage variations. Also, the subthreshold characteristics of these junction field‐effect transistors are presented. The behavior in the subthreshold region is found to be excellent.

Investigations of an Antimony Doped Poly-Silicon Gate Structure for P-Type JFET Applications

A polysilicon gate structure for application as gate material in p-channel JFETs is presented. The structure was manufactured using solid-phase epitaxy of an evaporated antimony/amorphous—silicon layer. The fabrication process together with experimental evaluation of both diode and JFET characteristics is given. The structure shows near ideal n + p-junction behaviour and the fabricated JFETs are normally off with good values of subthreshold swing and transconductance.