Herman Schmit

Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper

Intels Xeon roadmap includes package-integrated FPGAs in every new generation. In this talk, we will dissect why this is such a powerful combination at this time of great change in datacenter workloads. We will show how power savings within the CPU complex is a significant multiplier for power savings in the datacenter as a whole. Focusing on the domain of machine learning, we will present the recent evolution of data types and operators, and make the case that FPGAs are the path to facilitate this continued evolution. Finally, we will discuss the criticality of the close coupling of the CPU and the FPGA. This coupling facilitates high bandwidth and low latency communication that is required for the development, debugging and deployment of heterogeneous applications.

3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration

A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceivers were reused enabling a transceiver roadmap independent of FPGA fabric. Fig. 3.3.2 shows a 560mm2 fabric die and six transceiver dice. The programmable fabric contains 2.8M logic elements, DSP, memory components, and routing interconnect operating at up to 1GHz. Applications drove the need for improved flexibility and security of the FPGA configuration system. A triple-modular redundant microprocessor-based secure device manager (SDM) was designed and is programmed by embedded software.