Hermann F. Uhlmann

Design centering methods for yield optimization of cryoelectronic circuits

We present the results of comparison of different design centering methods, e.g. simplicial approximation method and centers-of-gravity method. The effectiveness of the proposed yield optimization strategies is demonstrated by application to various RSFQ circuits and analytical test functions. A SPICE-type program which includes the possibilities of analog behavior modeling and transient noise simulation was used for circuit simulation. Based on these methods, an interactive yield optimization framework for cryo-electronic circuits was developed and tested.

Formal description of the functional behavior of RSFQ logic circuits for design and optimization purposes

For being used in the design of Rapid Single Flux Quantum (RSFQ) circuits in a multipurpose manner, we developed a systematic and consistent approach for modeling the nominal circuit behavior using hardware description languages. We are presenting a method for establishing evaluation criteria for the circuits behavior which can directly be used in the input for circuit simulation and serve as a behavioral reference in yield-driven optimization cycles. Furthermore, this behavioral modeling technique allows for mixed-mode simulation with its advantages of both analysis speed-up and error localization. Finally, we demonstrate the application in high-level circuit synthesis which will be necessary to manage complex design problems.

Noise analysis for intrinsic and external shunted Josephson junctions

In the design of electronic applications (for example, rapid single flux quantum (RSFQ) circuits), the properties of Josephson junctions (JJs) provided by technology are the major requirement. The characteristic voltage IcRn an dt he dynamic parameter βc are non-negligibly important, bu tt he external shunted junctions are only completely described by including the parasitic inductance between the junction area and the shunt resistor. The first publications of the RSFQ circuit technique were closely followed by many studies on the dynamic influence of this inductance. It has been pointed out that no practical value of this parameter has to be taken into account in the circuit design and optimization process. The operation of RSFQ logic circuits made of high-temperature superconductors (HTS) are strongly influenced by thermal noise. Our paper contains the determination of the digital bit-error rate for all different types of JJs by using a Fokker–Planck equation for describing the influence of thermal fluctuations. Ou ra nalysis shows that the parasitic inductance cannot be neglected in terms of noise. The intrinsic shunted junctions like high current density-, SINIS- and all kinds of HTS-JJs provide the best noise immunity for a fixed temperature.

A general approach for determining the switching probability in rapid single flux quantum logic circuits

A major restriction in the development of a working Rapid Single Flux Quantum (RSFQ) logic circuit with high-Tc superconductors is given by the influence of thermal noise. This gives reason to ask for a general determination of the digital bit error rate. As other approaches, our method of calculating the switching probability is based on the Fokker-Planck equation. In the past few years the bit error rates for a single Josephson junction, SQUIDs and the comparator were calculated by using this theory. We demonstrate numerical solution of the multidimensional Fokker-Planck equation to calculate bit error rates due to thermal noise for a Toggle Flip Flop circuit. In the present work, we combine thermal noise analysis with the effects of process variations in order to derive rules for designing high-Tc RSFQ logic circuits.

Minimization of noise-induced bit error rate in a high Tc superconducting dc/single flux quantum converter

The thermally induced bit error rate of a rapid single flux quantum logic circuit is theoretically examined using the Fokker–Planck equation. The error rate versus design parameters of a high Tc dc/single flux quantum converter is derived. In comparison with other design methodologies, a vanishingly small error rate at optimal parameters can be achieved.

Design tools for parameter determination and simulation of integrated Josephson structures

The recent development of integrated Josephson circuits with increased complexity-e.g. RSFQ devices-invokes the need of a comprehensive computer-aided design support. The derivation of circuit parameters from layout data as well as an efficient and versatile simulation technique are essential means in the design and dimensioning of complex integrated structures. We present a comprehensive solution for calculating circuit parameters and simulating the device dynamics. The calculation of inductances and capacitances is performed by three-dimensional field computation using special developed programs which have been proven in high-T/sub c/ SQUID design. They can process layout information in standard graphic interchange formats (e.g. DXF). The netlists for device simulation can be generated automatically from the equivalent circuit schematic. Additionally, a technique for distributed simulation, which allows performing margins-and-yields-analyses in an efficient manner, was elaborated. The performance of the whole design tool set is demonstrated using basic RSFQ circuits.<<ETX>>

Effects of a 20 K operation on the bit-error rates of a prospective MgB2 based digital circuit

The discovery of the superconductive properties of magnesium diboride enables us to attempt to produce a rapid single flux quantum (RSFQ) logic device with an operation temperature of about 20 K which can be easily reached with cryocoolers. As elevated temperatures significantly increase the probability of noise-induced errors, we examine the situation in this particular temperature range. We calculate bit-error rates (BER) due to thermal noise for a toggle flip-flop as a typical RSFQ circuit with a clock frequency of 100 GHz. For this, we consider parameter spread and noise separately and observe a very low noise-induced BER. The critical margin diminishes by a small amount only.

Design of HTS RSFQ circuits

Abstract After more than a decade of research in single flux quantum (SFQ) circuits, a high level of understanding the requirements for designing them with high-Tc superconductors (HTS) has been gained. Recently, the fabrication processes are being developed to be more and more in accordance with practical requirements for the design of real digital circuits. The contribution describes the complex relationship of desired high operation temperature and required low bit-error probability on a quantitative level. Suitable guidelines for circuit dimensioning are given. The discussion is oriented at one of the contemporary technological approaches. It is concluded that, despite some previous estimations, HTS SFQ circuits can work stable theoretically also at a relatively high operation temperature.

Modeling and analysis of capacitances in metallic single electron tunneling structures

The calculation of the capacitances between well-separated thin coplanar electrodes is of fundamental importance in single charge electronics, e.g. for optimizing the geometry of digital circuits with respect to desired coupling as well as to parasitic cross-talk capacitances. We are able to extract such capacitances from three-dimensional numerical field computations basing on the boundary element method. Our program yields relevant information about the dependence of the capacitance on geometry as verified by comparing calculated gate coupling capacitances of different types of single electron transistors with values obtained from the experiment.

Design issues for interconnects in densely packaged RSFQ structures

The manufacturing process of LTS RSFQ circuits is quite similar to that of the semiconductor chips, thus providing the possibility of an ultra high-density packaging similar to the modern semiconductor logic circuits. However, the miniaturization of the interconnects does not enhance their performance. The present work highlights the impact of the parasitic interactions between the superconductive interconnects on the correct logical functionality and the upper bias current margins of the LTS RSFQ circuits.