Hesham Hallal

Antipattern-based detection of deficiencies in Java multithreaded software

We investigate an antipattern-based approach to analyze Java multithreaded (MT) programs. We present a library of 38 antipatterns, which describe predefined recognized sources of multithreading related errors in the code. The antipatterns are archived in practical, easy to use templates, and are classified according to their potential effects on the program behavior. We also report on our experience in using these antipatterns in the analysis of real multithreaded applications.

Dynamic analysis of java applications for multithreaded antipatterns

Formal verification is not always applicable to large industrial software systems due to scalability issues and difficulties in formal model and requirements specification. The scalability and model derivation problems could be alleviated by runtime trace analysis, which combines both testing and formal verification. We implement and compare an ad-hoc custom approach and a formal approach to detect common bug patterns in multithreaded Java software. We use the tracing platform of the Eclipse IDE and state-of-the-art model checker Spin.

An automata-based approach to property testing in event traces

We present a framework for property testing where a partially ordered execution trace of a distributed system is modeled by a collection of communicating automata. We prove that the model exactly characterizes the causality relation between the events in the observed trace. We present the implementation of this approach in SDL, where ObjectGEODE is used to verify properties, and illustrate the approach with an industrial case study.

A formal approach to property testing in causally consistent distributed traces

A formal framework for the analysis of execution traces collected from distributed systems at run-time is presented. We introduce the notions of event and message traces to capture the consistency of causal dependencies between the elements of a trace. We formulate an approach to property testing where a partially ordered execution trace is modeled by a collection of communicating automata. We prove that the model exactly characterizes the causality relation between the events/messages in the observed trace and discuss the implementation of this approach in SDL, where ObjectGEODE is used to verify properties using model-checking techniques. Finally, we illustrate the approach with industrial case studies.

Inferring Behavioural Models from Traces of Business Applications

We present an approach to the inference of automata models of web-based business applications using only execution traces recording the externally observable behavior of such applications. The proposed approach yields behavioral models representing both the control flow of an application and the data variations corresponding to different types of users. We also describe how the obtained models allow the use of verification techniques like model checking in the validation phase using a case study featuring a travel reservation agency.

Verifying trustworthiness requirements in distributed systems with formal log-file analysis

The paper reports on an analysis technology based on the tracing approach to test trustworthy requirements of a distributed system. The system under test is instrumented such that it generates events at runtime to enable reasoning about the implementation of these requirements in a later step. Specifically, an event log collected during a system run is converted into a specification of the system. The (trustworthy) requirements of the system must be formally specified by an expert who has sufficient knowledge about the behaviour of the system. The reengineered model of the system and the requirement descriptions are then processed by an off-the-shelf model checker. The model checker generates scenarios that visualize fulfilments or violations of the requirements. A complex example of a concurrent system serves as a case study.

Design of divergence-free protocol converters using supervisory control techniques

In this paper, we use supervisory control techniques to design a protocol converter, which avoids divergence in a communication systems. A typical application is to design gateways that interface heterogeneous computer networks while minimizing the communication time with the involved parties. As an example, we design a divergence-free converter that interfaces an alternating bit sender and a non-sequenced receiver, and we implement the converter as an asynchronous circuit.