Radu Negulescu

Verification of speed-dependences in single-rail handshake circuits

A way to reduce the cost (area) or increase the performance of asynchronous circuits is to make timing assumptions that go beyond the isochronic fork. This, however, results in circuits that are not speed-independent. Such timing assumptions often boil down to imposing that, of two circuit paths that start at the same point, one path is faster than the other. We call speed-dependences of this form chain constraints, and we handle them as processes in a metric-free formalism. This paper applies chain constraints to verify single-rail handshake circuits in the context of their timing assumptions, and to evaluate safety margins for delay fluctuations. We discuss the lessons learned, including decomposition and weakening of extended isochronic fork assumptions, usage of CMOS cell models in the presence of hazards, and correlations between our discrete-state results and analog simulations.

Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip

In this paper we propose a novel refinement-based technique to formally verify data transfer in an asynchronous timing framework. Novel data transfer models are proposed to represent data communication between two locally independent clock domains. As a case study, we apply our technique to verify data transfer in a previously published architecture for globally asynchronous locally synchronous on-chip systems. In this case study, we find several race conditions, hazards, and other dangers that were not mentioned in the original publication, and we find additional delay constraints that avoid some of the detected dangers.

Formal verification of pulse-mode asynchronous circuits

This paper addresses the problem of verifying pulse-mode asynchronous circuits, which combine advantages of different asynchronous design styles. A novel technique is proposed for constructing in a modular manner specifications and functional models of pulse-mode circuits. Case studies show the feasibility of formal verification on the basis of the proposed construction, integrated into an existing technique for verifying synchronous circuits under relative timing constraints at several levels of abstraction.

Design of divergence-free protocol converters using supervisory control techniques

In this paper, we use supervisory control techniques to design a protocol converter, which avoids divergence in a communication systems. A typical application is to design gateways that interface heterogeneous computer networks while minimizing the communication time with the involved parties. As an example, we design a divergence-free converter that interfaces an alternating bit sender and a non-sequenced receiver, and we implement the converter as an asynchronous circuit.

Semi-hiding operators and the analysis of active-edge specifications for digital circuits

We propose to model and analyze active-edge specifications by a new concurrency operator, called semi-hiding. We define semi-hiding formally, study its algebraic properties, and overview several of its applications, such as interface recasting and tests of compliance for several asynchronous protocols. Semi-hiding and the related applications are integrated in a tool that supports automatic verification at several levels of abstraction.

Relative liveness: from intuition to automated verification

We define a new liveness condition for asynchronous circuits. Although finitary (finite-execution) descriptions are not powerful enough to express general liveness properties, those liveness properties needed in practice appear to be related in a unique manner to finitary descriptions. Our liveness condition exploits this observation and is defined directly on finitary descriptions, in two forms: one on finite trace structures and the other on finite automata. We prove the equivalence of these two forms. We also introduce a safety condition and derive theorems for the modular and hierarchical verification theorems of both safety and liveness. Finally, we give an algorithm for verifying our liveness condition.

Event-driven verification of switch-level correctness concerns

We propose a technique for the verification of MOS circuits, focusing on signal transitions (events) rather than signal levels. Diverse conditions, behaviors, and even delay assumptions are modeled as processes that can be coupled and compared to circuit specifications in a unified formalism. Verification is performed modularly and hierarchically by a BDD-based tool. We illustrate this technique on a self-timed RAM.

Bolstering faith in GasP circuits through formal verification

We propose a refinement-based technique to formally verify circuits of the GasP family. Verifying GasP circuits presents two main challenges: exploit their highly modular structure to reduce verification costs, and express formally their unconventional behavior at the low level, such as bidirectional signals, self-resetting logic, and fights. We propose a novel semi-automated technique for constructing specification models for interfaces of GasP circuit control units, which synchronize single-track handshake signals from different channels. These specifications are captured at a high level using abridged data transition events and transformed into intermediate specifications using low-level signal transition events. High-level verifications using data transition events are exact if each unit conforms to its intermediate specification. As a case study, we verify that a set of relative timing constraints inside the units and along channels between units, consistent with the original sizing of the circuits, is sufficient to guarantee correctness of a previously proposed square FIFO.

Refinement-based formal verification with heterogeneous timing

Abstract.In this paper we propose a refinement-based technique to formally verify data transfer in a heterogeneous timing framework. Novel data transfer models are proposed to represent data communication between two locally independent clock domains via an asynchronous handshake environment. As a case study, we apply our technique to automatically verify data transfer in a previously published architecture for globally asynchronous locally synchronous on-chip systems. In this case study, we find several race conditions, hazards, and other dangers that were not mentioned in the original publication, and we find additional delay constraints that avoid some of the detected dangers.

Automata of asynchronous behaviors

We survey three applications that use finite automata to specify behaviors of concurrent processes in general, and asynchronous circuits in particular. The applications are: verification of concurrent processes, liveness properties, and delay-insensitivity of asynchronous networks. In all three cases, we start with a common model of a nondeterministic finite automaton, and then add certain application-specific features. Typically, the added features involve separating the alphabet or the state set of the automaton into several disjoint subsets. For each application we provide the motivation, describe the type of automaton used, define the most important operations, and state some of the key results. For process verification, we describe a BDD-based tool that implements the respective automata and operations.