Hideaki Numata

A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield

We have developed a Josephson 4-Kbit RAM with improved component circuits and a device structure having two Nb wiring layers. A resistor coupled driver and sense circuit are improved to have wide operating margins. The fabrication process is simplified using bias sputtering, as a result, its reliability is increased. The RAM is composed of approximately 21000 Nb/AlO/sub x//Nb Josephson junctions, Mo resistors, Nb wirings, and SiO/sub 2/ insulators. Experimental results show a minimum access time of 380 ps and power dissipation of 9.5 mW. Maximum bit yield of 84% is obtained in minimum magnetic field of about 20 /spl mu/G. We confirm that most of fail bits are caused by trapped magnetic flux, and the RAM functions properly for 98% of the memory cells after measuring fail bit map several times.<<ETX>>

High-frequency clock operation of Josephson 256-word/spl times/16-bit RAMs

A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.

Scalable Cell Technology Utilizing Domain Wall Motion for High-speed MRAM

We propose a new MRAM cell that stores data in the form of the domain wall (DW) position. The DW is moved by the spin-polarized current that flows in the free layer. The cell was fabricated and the writing characteristics were investigated. A writing current of the cell was scalable, and the current density was reduced by using a new material. The cell is suitable for a high-speed MRAM that will compete with an eSRAM.

Bit yield improvement by precise control of stray fields from SAF pinned layers for high-density MRAMs

A write-operating window with a 100% functional bit yield was successfully obtained by the control of stray fields from synthetic antiferromagnetic (SAF) pinned layers in conventional magnetic random access memories with rectangular magnetic tunneling junction bits. The stray fields were controlled by a newly developed ion-beam etching technique without causing damage and by a precise setting of the SAF pinned layer thickness, and are balanced with Neel coupling fields. As a result, it was found that symmetric switching astroid curves with no offset were obtained and switching distributions were minimized at the zero offset field.

A 16-Mb Toggle MRAM With Burst Modes

This paper describes a recently developed 16-Mb toggle magnetic random access memory (MRAM). It has 100-MHz burst modes that are compatible with a pseudo-SRAM even though the toggle cell requires reading and comparing sequences in write modes. To accelerate operating clock frequency, we propose a distributed-driver wide-swing current-mirror scheme, an interleaved and pipelined memory-array group activation scheme, and a noise-insulation switch scheme. These circuit schemes compensate the toggle cell timing overhead in write modes and maintain write-current precision that is essential for the wide operational margin of MRAMs. Because toggle cells are very resistant to write disturbance errors, we designed the 16-Mb MRAM to include a toggle MRAM cell. The MRAM was fabricated with 0.13-mum CMOS and 0.24-mum MRAM processes with five metal layers.

MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current (MRC) is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write (MW) failures from degrading 1Gb MRAM yield where the standard deviation of MRC variation from other origins is less than 5%.

Investigation of SFQ integrated circuits using Nb fabrication technology

In NECs standard process, the minimum junction size is 2 µm and the critical current density (JC) is 2.5 kA cm-2. In the process, i-line stepper lithography and reactive ion etching with SF6 gas are used and the standard deviation () of the critical current (IC) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an IC variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.

Highly Uniform Thin-Film Transistors Printed on Flexible Plastic Films with Morphology-Controlled Carbon Nanotube Network Channels

Carbon nanotube (CNT) transistor arrays were fabricated on plastic films by printing. All the device elements were directly patterned by maskless printing without any additional patterning process, and minimum materials were used. During fabrication, the morphology of the CNT random network was controlled by an adsorption mechanism on the surface to be printed, which resulted in excellent and uniform electrical properties. The field-effect mobility was further improved by post-treatment to modify the morphology of the CNT network. These results are promising for realizing printed electronics integrated with CNT transistors.

Magnetic configuration of submicron-sized magnetic patterns in domain wall motion memory

We observed magnetic configuration and its change by external magnetic fields in submicron-sized U- and H-shaped NiFe patterns with an x-ray magnetic circular dichroism photoemission electron microscope. The microscope images showed the formation of a single domain wall (DW) with transverse structure at one corner of the U- and H-shaped patterns by applying the magnetic field from the oblique direction. By applying the magnetic field from the direction parallel to a horizontal bar in the patterns, the magnetic configuration in the U-shaped pattern was changed and four patterns were formed: (1) the DW moved from one trap site to another, (2) the DW moved beyond the trap site and formed a single domain, (3) the DW moved and stopped between the trap sites, and (4) the DW remained at the initial position. Only pattern (1) showed reversible DW motion, although pattern (2) was predominantly formed. In contrast, the magnetization configurations showed pattern (1), and reversible DW motion was observed for more t...

Superconducting digital electronics

Superconducting devices have intrinsically superior characteristics to those of semiconductor devices. Presently, we can fabricate more than twenty thousand junctions on one chip using niobium technology. We have demonstrated the operation of a network system with a superconducting interconnection chip using voltage-state logic. Single flux quantum devices are promising for future superconducting applications because the clock frequency of SFQ logic is higher than that of voltage-state. We have proposed a high-end switch based on hybrid architecture using optical devices, semiconductors and SFQ devices. To demonstrate the high-speed operation of SFQ circuits, we developed an arbiter circuit that uses SFQ components and the arbiter circuit operates at 60 GHz. We also have developed a high Tc superconducting (HTS) SFQ sampler system for observing ultra-fast signal waveforms. In addition, we will discuss the prospects of future superconducting devices based on the fabrication technologies we developed.