Shuichi Tahara

A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield

We have developed a Josephson 4-Kbit RAM with improved component circuits and a device structure having two Nb wiring layers. A resistor coupled driver and sense circuit are improved to have wide operating margins. The fabrication process is simplified using bias sputtering, as a result, its reliability is increased. The RAM is composed of approximately 21000 Nb/AlO/sub x//Nb Josephson junctions, Mo resistors, Nb wirings, and SiO/sub 2/ insulators. Experimental results show a minimum access time of 380 ps and power dissipation of 9.5 mW. Maximum bit yield of 84% is obtained in minimum magnetic field of about 20 /spl mu/G. We confirm that most of fail bits are caused by trapped magnetic flux, and the RAM functions properly for 98% of the memory cells after measuring fail bit map several times.<<ETX>>

A single flux quantum standard logic cell library

To expand designable circuit scale, we have developed a new cell-based circuit design for single flux quantum (SFQ) circuit. We call it CONNECT cell library. The CONNECT cell library has over 100 cells at present. Each CONNECT cell consists of a Verilog digital behavior model, circuit information, and a physical layout. All circuit parameter values have been optimized for obtaining the widest margins and minimizing interactions between cells. At the layout level, we have defined a minimum standard cell size and made cell height and width a multiple of the size. Using this cell library, we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. For estimation of the reliability of the library, we designed and fabricated test circuits using CONNECT cells. We demonstrated experimentally correct operations, which means the CONNECT cell library is sufficiently reliable.

High-temperature superconducting edge-type Josephson junctions with modified interface barriers

This paper describes recent results on the fabrication, electrical characteristics, and microstructure of high-temperature superconducting edge-type Josephson junctions with modified interface barriers. The barriers are formed by surface modification of the YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// base layer. This process involves structural and chemical modification by ion irradiation and crystallization by annealing. The junctions showed resistively and capacitively shunted junction-like current-voltage characteristics and excellent uniformity. The spread in the critical current for one hundred junctions was smaller than 1/spl sigma/=10% at 4.2 K. The uniformity is now approaching 1/spl sigma/=5%. The junction characteristics have remained the same after two-year room-temperature storage. They also showed no change after high-temperature processing at about 700/spl deg/C. High-resolution transmission electron microscopy revealed that both the crystal structure and chemical composition in relatively thick barriers are different from those of YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta//.

MRAM Cell Technology for Over 500-MHz SoC

This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 mum2, which is smaller than the SRAM cell area, in the 0.13-mum CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kOmega and the magnetoresistive (MR) ratio is more than 70%

An integration of all refractory Josephson logic LSI circuit

An integration process for the fabrication of an all refractory Josephson LSI logic circuit is described. In this process, niobium nitride and niobium double-layered Josephson junctions were integrated using a reactive ion etching with a 2.5 μm minimum feature. A highly selective and anisotropic RIE process and a planarizing technology have been developed for intagrating a circuit with LSI complexity. For evaluating the process capability, test vehicle circuits with MSI/LSI level complexity have been designed and fabricated using this process. An 8 bit ripple carry adder and a 4×4 bit parallel multiplier have been integrated with Josephson four junction logic ( 4JL ) gates, the largest of which contains more than 2800 Josephson junctions. Both functionality and high-speed performance testings have been successfully performed with these test circuits.

570-ps 13-mW Josephson 1-kbit NDRO RAM

Josephson 1-kbit random access memories (RAMs) have been fabricated using Nb multilayer planarization technology with Nb/AlO/sub x//Nb junctions and Mo resistors. The RAM design has been reported previously. The RAM consists of a 32*32-bit nondestructive readout (NDRO) memory cell array and peripheral circuits. The NDRO memory cell consists of a loop storing three flux quanta and two 3-junction interferometer gates. The peripheral circuits consist of decoders with address inverters, drivers, a sense circuit and reset circuits, where resistor-coupled Josephson logic (RCJL) circuits are used as basic circuits. The RAM circuit size is 4.4*4.4 mm/sup 2/, and the memory cell size is 65*65 mu m/sup 2/. About 10000 Nb/AlO/sub x//Nb junctions with 1030-A/cm/sup 2/ critical current density were contained in the RAM. Minimum line and space widths were 3 and 2 mu m, respectively. The Mo resistors had 1.2 approximately 1.3 Omega sheet resistance. About 40 percent of the bits were successfully operated with a +or-18-percent bias margin. A minimum 570-ps access time with 13-mW power dissipation was obtained for the highest peripheral circuit bias conditions. >

A 4-kbit Josephson nondestructive read-out RAM operated at 580 psec and 6.7 mW

A fully decoded 4-kb Josephson nondestructive readout high-speed RAM with vortex transitional memory cells was designed and operated successfully. The 4-kb Josephson RAM is composed of 64-b*64-b cells, polarity-convertible drivers, address decoders using resistor coupled Josephson logic (RCJL) gates, and a resistively loaded sense circuit. The memory cells use vortex transitions in their superconducting loops for writing and reading data. The cells are activated by two control signals without timing control, while all peripheral circuits are activated by an AC power supply. This memory configuration eliminates the timing sequence needed for memory operations, resulting in a decrease in the memory operation time for an actual memory chip. The 4-kb Josephson high-speed RAM was fabricated using niobium planarization technique with a 1.5- mu m design rule. The RAM circuit size is 4.8*4.8 mm/sup 2/ and the memory cell is 55*55 mu m/sup 2/. More than 25000 Nb-AlO/sub x/-Nb Josephson junctions with approximately 1200 A/cm/sup 2/ critical current density are contained in the RAM chip. An access time of 580 ps and a power consumption of 6.7 mW are obtained for the nondestructive memory operation.

Magnetic Tunnel Junction (MTJ) Patterning for Magnetic Random Access Memory (MRAM) Process Applications

We have developed a top free type magnetic tunnel junction (MTJ) patterning technique that involves tunnel barrier etching with enough time margins for chemical assisted ion etching (CAIE). The approximately 1 nm thick tunnel barrier enables stopping the etching process in a shorter time margin. We have found that no aluminum-oxide barrier shorting by re-deposition occurred in chlorine based CAIE, when the etching depth into anti-ferromagnetic IrMn layer was less than 5 nm. The magnetoresistance (MR) ratio of the whole MTJ patterns reached 35% on a 6-inch wafer. The time margin of the etching was 120 s, which is long enough for an magnetic random access memory (MRAM) process.

High-performance and damage-free magnetic film etching using pulse-time-modulated Cl/sub 2/ plasma

Magnetic films have been used to fabricate magnetic random access memory (MRAM) devices. A key issue for producing magnetic devices is the problems associated with magnetic film etching, in particular a low etching rate and sidewall deposition caused by non-volatile etching products. We recently found that plasma radiations degraded magnetic properties. To overcome these problems, we investigated the effects of a few tens of micro-second pulse-time-modulated (TM) plasma on magnetic film etching. In this study, we found that injecting negative ions from TM plasma produced no sidewall deposition and accomplished damage-free magnetic film etching.

High-frequency clock operation of Josephson 256-word/spl times/16-bit RAMs

A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.