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Dive into the research topics where Hideharu Amano is active.

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Featured researches published by Hideharu Amano.


field-programmable logic and applications | 2004

Stochastic Simulation for Biochemical Reactions on FPGA

Masato Yoshimi; Yasunori Osana; Tomonori Fukushima; Hideharu Amano

Biological cell simulations generally require high-powered computer resources. A reconfigurable system is a possible solution to the problem as an alternative approach against PC/WS clusters. A stochastic simulation algorithm proposed by Gillespie is implemented on a reconfigurable platform called ReCSiP, and the performance is evaluated. The implemented Lotka system outperforms the software implementation on AthlonXP2800+ by 105.13 times.


field-programmable technology | 2005

The design of scalable stochastic biochemical simulator on FPGA

Masato Yoshimi; Yasunori Osana; Yow Iwaoka; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Naoki Iwanaga; Hiroaki Kitano; Hideharu Amano

Biochemical simulations including whole-cell models require high performance computing systems. Reconfigurable systems are expected to be an alternative solution for conventional methods by PC clusters or vector computers. This paper shows the implementation of a stochastic biochemical simulation algorithm called Next Reaction Method for Virtex-II PRO. As the result of benchmarking with a small reaction system, the FPGA-based simulator outperforms the software implementation on Xeon 2.40 GHz by 17.1 times


field-programmable logic and applications | 2005

Efficient scheduling of rate law functions for ODE-based multimodel biochemical simulation on an FPGA

Naoki Iwanaga; Yuichiro Shibata; Masato Yoshimi; Yasunori Osana; Yow Iwaoka; Tomonori Fukushima; Hideharu Amano; Akira Funahashi; Noriko Hiroi; Hiroaki Kitano; Kiyoshi Oguri

A reconfigurable biochemical simulator by solving ordinary differential equations has received attention as a personal high speed environment for biochemical researchers. For efficient use of the reconfigurable hardware, static scheduling of high-throughput arithmetic pipeline structures is essential. This paper shows and compares some scheduling alternatives, and analyzes the tradeoffs between performance and hardware amount. Through the evaluation, it is shown that the sharing first scheduling reduces the hardware cost by 33.8% in average, with the up to 11.5% throughput degradation. Effects of sharing of rate law functions are also analyzed.


field-programmable logic and applications | 2006

An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems

Masato Yoshimi; Yasunori Osana; Yow Iwaoka; Yuri Nishikawa; Toshinori Kojima; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Naoki Iwanaga; Hiroaki Kitano; Hideharu Amano

Stochastic simulation of biochemical systems has become one of major approaches to study life processes as system, yet is a computational challenge to run the simulation due to its vast calculation cost. This paper shows the implementation and evaluation of a stochastic simulation algorithm (SSA) called first reaction method on an FPGA-based biochemical simulator. It achieves high throughput by (1) consecutively throwing data into deeply-pipelined floating point arithmetic units, and (2) by distributing multiple simulators for parallel execution. As the result of evaluation on an FPGA-based simulation platform called ReC-SiP2, the simulator outperforms execution on Xeon 2.80 GHz by approximately 80 times, even with large-scale biochemical systems


network on chip architectures | 2010

A variable-pipeline on-chip router optimized to traffic pattern

Yuto Hirata; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano

Network-on-Chip (NoC) can be evaluated from various aspects, such as communication latency, throughput, and power consumption. The preference of these requirements depends on each application. An on-chip variable-pipeline (VP) router that can adapt to these requirements by dynamically reconfiguring its data path structure is proposed in this paper. In response to the communication pattern, it can change the pipeline structure, supply voltage, and operational frequency using the dynamic voltage and frequency scaling (DVFS). As the traffic load becomes high, the VP router uses a look-ahead two-cycle pipeline structure for exploiting the maximum frequency, while it behaves as a one-cycle router when a low latency is preferred. A three-cycle pipelined structure with an adaptive routing enables to dynamically avoid hotspots. Instead of a simple pipeline-stage unification which causes rapid decrease of the operating frequency, by speculatively executing multiple pipeline stages in parallel, the operating frequency gracefully decreases as the number of the pipeline stages increases. Simulation results show that the one-cycle mode offers the shortest communication latency, while the two-cycle mode achieves the highest throughput for SPLASH-2 benchmarks.


field-programmable logic and applications | 2003

Implementation of ReCSiP: A ReConfigurable cell SImulation Platform

Yasunori Osana; Tomonori Fukushima; Hideharu Amano

A reconfigurable accelerator for cell simulators called ReCSiP is proposed. It consists of both reconfigurable hardware and software platform. For high performance simulation, numerical solution of kinetic formulas, which require a large amount of computation, are processed on the reconfigurable hardware. It also provides programming interface for developing cell simulators. In this paper, Michaelis-Menten solver is designed and implemented on ReCSiP. The result of preliminary evaluation shows that ReCSiP is 8 times faster than Intel PentiumIII 1.13GHz when simple metabolic simulations are executed.


asia and south pacific design automation conference | 2004

ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA

Yasunori Osana; Tomonori Fukushima; Hideharu Amano

ReCSiP is a reconfigurable accelerator which was designed for biocomputing. The first application described here is a kinetic simulation of metabolic systems, and the second one is an image processing accelerator. Both of can sufficient replace small PC/WS clusters.


international parallel and distributed processing symposium | 2005

An FPGA-based, multi-model simulation method for biochemical systems

Yasunori Osana; Tomonori Fukushima; Masato Yoshimi; Yow Iwaoka; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Hiroaki Kitano; Hideharu Amano

Modeling and simulation of a cellular system on computers are now becoming an essential process in biological researches. However, modern PCs cant provide enough performance to simulate large-scale biochemical networks. ReCSiP is the alternative FPGA-based solution for biochemical simulations. In this paper, the novel method of biochemical simulation with multiple reaction models on an FPGA is proposed. The method generates optimal circuit and its optimal schedule for each simulation models written in SBML, the standard markup language in systems biology. ReCSiP has a Xilinxs XC2VP70 and achieved over 20-fold speedup compared to Intels Pentiumlll 1.13GHz.


field-programmable logic and applications | 2006

Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip

Yasunori Osana; Masato Yoshimi; Yow Iwaoka; Toshinori Kojima; Yuri Nishikawa; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Naoki Iwanaga; N. Kitano; Hideharu Amano

ReCSiP is an FPGA-based biochemical simulator to accelerate kinetic simulations of biochemical pathways. Biochemical models are described as a set of ordinary differential equations (ODEs). Each equation in the model is called rate law function, which represents the velocity of corresponding biochemical reaction mechanism. ReCSiP achieves high-throughput simulation with statically pipelined rate law function modules and numerical integration modules on an FPGA. This paper shows the basic structure of ReCSiP, and results of evaluation in 2 aspects: area and throughput. As the summary of evaluation, 1) about 64% of the total circuit area is occupied by floating-point arithmetic units, and 2) with an XC2VP70, ReCSiP at 90MHz can achieve 20times or more speedup compared to Intels Pentium4 microprocessor at 3.2GHz


ERSA | 2006

A Parametric Study of Scalable Interconnects on FPGAs.

Daihan Wang; Hiroki Matsutani; Masato Yoshimi; Michihiro Koibuchi; Hideharu Amano

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Hiroaki Kitano

Okinawa Institute of Science and Technology

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