Yow Iwaoka
Keio University
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Publication
Featured researches published by Yow Iwaoka.
field-programmable logic and applications | 2007
M. Yoshiini; Yow Iwaoka; Yuri Nishikawa; Toshinori Kojima; Yasunori Osana; Yuichiro Shibata; Naoki Iwanaga; Hideki Yamada; Hiroaki Kitano; Akira Funahashi; Noriko Hiroi; Hideharu Amano
This paper introduces a scalable FPGA implementation of a stochastic simulation algorithm (SSA) called the next reaction method. There are some hardware approaches of SSAs that obtained high-throughput on reconfigurable devices such as FPGAs, but these works lacked in scalability. The design of this work can accommodate to the increasing size of target biochemical models, or to make use of increasing capacity of FPGAs. Interconnection network between arithmetic circuits and multiple simulation circuits aims to perform a data-driven multi-threading simulation. Approximately 8 times speedup was obtained compared to an execution on Xeon 2.80 GHz.
field-programmable technology | 2005
Masato Yoshimi; Yasunori Osana; Yow Iwaoka; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Naoki Iwanaga; Hiroaki Kitano; Hideharu Amano
Biochemical simulations including whole-cell models require high performance computing systems. Reconfigurable systems are expected to be an alternative solution for conventional methods by PC clusters or vector computers. This paper shows the implementation of a stochastic biochemical simulation algorithm called Next Reaction Method for Virtex-II PRO. As the result of benchmarking with a small reaction system, the FPGA-based simulator outperforms the software implementation on Xeon 2.40 GHz by 17.1 times
field-programmable logic and applications | 2005
Naoki Iwanaga; Yuichiro Shibata; Masato Yoshimi; Yasunori Osana; Yow Iwaoka; Tomonori Fukushima; Hideharu Amano; Akira Funahashi; Noriko Hiroi; Hiroaki Kitano; Kiyoshi Oguri
A reconfigurable biochemical simulator by solving ordinary differential equations has received attention as a personal high speed environment for biochemical researchers. For efficient use of the reconfigurable hardware, static scheduling of high-throughput arithmetic pipeline structures is essential. This paper shows and compares some scheduling alternatives, and analyzes the tradeoffs between performance and hardware amount. Through the evaluation, it is shown that the sharing first scheduling reduces the hardware cost by 33.8% in average, with the up to 11.5% throughput degradation. Effects of sharing of rate law functions are also analyzed.
field-programmable logic and applications | 2005
Yasunori Osana; Tomonori Fukushima; Masato Yoshimi; Yow Iwaoka; Hideharu Amano; Akira Funahashi; Noriko Hiroi; Hiroaki Kitano; Yuichiro Shibata; Naoki Iwanaga
Today, mathematical modeling and simulation of biochemical pathways take a major role in biological researches. However, modern microprocessors cannot provide enough throughputs to explore the large parameter space of target pathways. To address this problem, ReCSiP (a reconfigurable cell simulation platform), an FPGA-based biochemical simulator is proposed. Its an ODE-based simulator, which solves the rate-law functions. The framework proposed in this paper, enables to simulate pathways consisting many different types of chemical reactions by connecting the rate-law modules (solvers) on an FPGA. It provides the solver-to-solver communication mechanism on an FPGA and automatic configuration software to generate the circuit.
field-programmable logic and applications | 2007
Hideki Yamada; Naoki Iwanaga; Yuichiro Shibata; Yasunori Osana; Masato Yoshimi; Yow Iwaoka; Yuri Nishikawa; Toshinori Kojima; Hideharu Amano; Akira Funahashi; Noriko Hiroi; Hiroaki Kitano; Kiyoshi Oguri
In order to simulate large scale biological models with a reconfigurable FPGA-based biochemical simulator system, reduction of required resources are essential. This paper proposes a method which combines common terms in rate law functions appeared in biochemical models and generates a shared hardware module used for numerical integration. In this approach, two functions are combined in a tree structure level, followed by pipeline scheduling and arithmetic module binding. The evaluation result reveals that this approach reduces hardware resources by 31.4 % on average at the cost of 14.4 % throughput degradation.
Electronics and Communications in Japan Part Ii-electronics | 2007
Yasunori Osana; Masato Yoshimi; Yow Iwaoka; Toshinori Kojima; Yuri Nishikawa; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Naoki Iwanaga; Hiroaki Kitano; Hideharu Amano
field-programmable logic and applications | 2006
Masato Yoshimi; Yasunori Osana; Yow Iwaoka; Yuri Nishikawa; Toshinori Kojima; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Naoki Iwanaga; Hiroaki Kitano; Hideharu Amano
international parallel and distributed processing symposium | 2005
Yasunori Osana; Tomonori Fukushima; Masato Yoshimi; Yow Iwaoka; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Hiroaki Kitano; Hideharu Amano
field-programmable logic and applications | 2006
Yasunori Osana; Masato Yoshimi; Yow Iwaoka; Toshinori Kojima; Yuri Nishikawa; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Naoki Iwanaga; N. Kitano; Hideharu Amano
IEICE technical report. Computer systems | 2006
Yasunori Osana; Masato Yoshimi; Yow Iwaoka; Toshinori Kojima; Yuri Nishikawa; Akira Funahashi; Noriko Hiroi; Yuichiro Shibata; Naoki Iwanaga; Hiroaki Kitano; Hideharu Amano