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Dive into the research topics where Hidehiko Kita is active.

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Featured researches published by Hidehiko Kita.


international symposium on neural networks | 2009

Obstacle to training SpikeProp networks — Cause of surges in training process —

Haruhiko Takase; Masaru Fujita; Hiroharu Kawanaka; Shinji Tsuruoka; Hidehiko Kita; Terumine Hayashi

In this paper, we discuss an obstacle to training in SpikeProp[1], which is a type of supervised learning algorithms for spiking neural networks. In the original publication of SpikeProp, weights with mixed signs are suspected to cause failures of training. We pointed out the cause of it through some experiments. Weights with mixed signs make the dynamics of the units activity twisted, and the twisted dynamics break the assumption that SpikeProp algorithm is based on. Therefore, it causes surges in training processes. They would mean an underlying problem on training processes.


international symposium on neural networks | 2001

Weight minimization approach for fault tolerant multi-layer neural networks

Haruhiko Takase; Hidehiko Kita; Terumine Hayashi

We propose a new learning algorithm to enhance fault tolerance of multilayer neural networks (MLN). This method is based on the idea that strong connections make MLN sensitive to faults. To eliminate such connections, we introduce the new evaluation function for the new learning algorithm. It consists of not only the output error but also the sum of all squared weights. With the new evaluation function, the learning algorithm minimizes not only output error but also weights. The value of parameter to balance effects of these two terms is decided actively during training of MLN. Next, to show the effectiveness of the proposed method, we apply it to pattern recognition problems. It is shown that the miss recognition rate and the activity of hidden units are improved.


asia and south pacific design automation conference | 1997

An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits

Kai Zhang; Haruhiko Takase; Terumine Hayashi; Hidehiko Kita

This paper presents an enhanced iterative improvement method with multiple pins (EIIMP) to evaluate the maximum number of simultaneous switching gates. Although the iterative improvement method is a simple algorithm, it is powerful to this purpose. Keeping this advantage, we enhance it by two points. The first one is to change values for multiple successive primary inputs at a time. The second one is to rearrange primary inputs on the basis of the closeness that represents the number of overlapping gates between fan-out regions. Our method is shown to be effective by experiments for ISCAS benchmark circuits.


asian test symposium | 1994

A genetic approach to test generation for logic circuits

Terumine Hayashi; Hidehiko Kita; K. Hatayama

This paper presents a genetic algorithm to generate tests for logic circuits. Bit strings corresponding to primary input patterns are evolved into tests for detecting a target fault by genetic operations. Some new techniques, such as a crossover operation based on fault-excitability and fault-drivability, are introduced to achieve high fault coverage. Experimental results show that the genetic approach is effective for solving test generation problem.<<ETX>>


international symposium on neural networks | 2003

Effect of regularization term upon fault tolerant training

Haruhiko Takase; Hidehiko Kita; Terumine Hayashi

To enhance fault tolerance of multi-layer neural networks, we proposed PAWMA (partially adaptive weight minimization approach). This method minimizes not only output error but also the sum of squares of weights (the regularization term). This method aims to decrease the number of connections whose faults strongly degrade the performance of MLNs (important connections). On the other hand, weight decay, which aims to eliminate unimportant connections, is base on the same idea. This method expects to keeping important connections and decaying unimportant connections. In this paper, we discuss about the contradiction between two effects of the regularization term. Through some experiment, we show that the difference between two effects is brought by the partially application of the regularization term.


international symposium on neural networks | 2000

Evaluation function for fault tolerant multi-layer neural networks

Haruhiko Takase; Tsuyoshi Shinogi; Terumine Hayashi; Hidehiko Kita

We propose a new learning algorithm to enhance fault tolerance of multilayer neural networks (MLN). This method is based on the idea that strong weights make MLN sensitive to faults. The purpose of the proposed algorithm is to make weights as small as possible through its training. The evaluation function of the proposed algorithm consists of not only the output error but also the square sum of weights. With the new evaluation function the learning algorithm minimizes not only output error but also weights. We discussed about the value of parameter to balance effects of these two terms. Next, we apply it to pattern recognition problems. As a result, it is shown that the degradation of recognition ratio is improved.


Journal of Computer Science and Technology | 2005

On test data compression using selective don't-care identification

Terumine Hayashi; Haruna Yoshioka; Tsuyoshi Shinogi; Hidehiko Kita; Haruhiko Takase

This paper proposes an effective method for reducing test data volume under multiple scan chain designs. The proposed method is based on reduction of distinct scan vectors using selective don’t-care identification. Selective don’t-care identification is repeatedly executed under condition that each bit of frequent scan vectors is fixed to binary values (0 or 1). Besides, a code extension technique is adopted for improving compression efficiency with keeping decompressor circuits simple in the manner that the code length for infrequent scan vectors is designed as double of that for frequent ones. The effectiveness of the proposed method is shown through experiments for ISCAS’89 and ITC’99 benchmark circuits.


computational intelligence in robotics and automation | 2003

Manipulation of hidden units activities for fault tolerant multi-layer neural networks

Yusei Katsuda; Haruhiko Takase; Hidehiko Kita; Terumine Hayashi

We propose a new training algorithm to enhance fault tolerance of multi-layer neural networks (MLNs). This method is based on the fact that faults on connections between hidden layer and output layer have a harmful effect on fault tolerance of MLNs. to decrease these effects, we introduced two approaches, (1) reduce the number of strong connections between hidden layer and output layer, (2) neutralize the activities of hidden units. The first approach aims to reduce the undesirable connections. The second one aims to increase redundancy of internal representation.


Systems and Computers in Japan | 2001

An enhanced fault model for high defect coverage

Junzhi Sang; Tsuyoshi Shinogi; Haruhiko Takase; Hidehiko Kita; Terumine Hayashi

In this paper, we propose an enhanced fault model to increase coverage in detecting physical faults in LSI. First, as an alternative to the single stuck-at fault model, we propose the “single gate logical fault with Hamming distance 1” (SGLFH1) model, which is capable of generating test pattern sets that detect more defects from the same number of faults. The characteristics of this fault model are discussed and the effectiveness of the test pattern sets generated by it is described. Next we show that the multiple detection test pattern set for single stuck-at faults that is conventionally used to enhance defect coverage does not detect SGLFH1 faults satisfactorily. In addition, the effectiveness of the proposed model is shown by comparing the fault detection ratio of the SGLFH1 test pattern set for physical surrogate faults [1, 2] with the corresponding fault detection ratio of the multiple detection test pattern set for single stuck-at faults.


asian test symposium | 2006

Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing

Terumine Hayashi; Naotsugu Ikeda; Tsuyoshi Shinogi; Haruhiko Takase; Hidehiko Kita

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