Terumine Hayashi

A simple and efficient method for generating compact IDDQ test set for bridging faults

This paper presents an efficient method for generating a compact test set for IDDQ testing of bridging faults in combinational CMOS circuits. This method is based on the iterative improvement method. Though our method is simple and easy to implement, it is efficient. Experimental results for large ISCAS benchmark circuits demonstrate its efficiency in comparison with results of previous methods.

Obstacle to training SpikeProp networks — Cause of surges in training process —

In this paper, we discuss an obstacle to training in SpikeProp[1], which is a type of supervised learning algorithms for spiking neural networks. In the original publication of SpikeProp, weights with mixed signs are suspected to cause failures of training. We pointed out the cause of it through some experiments. Weights with mixed signs make the dynamics of the units activity twisted, and the twisted dynamics break the assumption that SpikeProp algorithm is based on. Therefore, it causes surges in training processes. They would mean an underlying problem on training processes.

Weight minimization approach for fault tolerant multi-layer neural networks

We propose a new learning algorithm to enhance fault tolerance of multilayer neural networks (MLN). This method is based on the idea that strong connections make MLN sensitive to faults. To eliminate such connections, we introduce the new evaluation function for the new learning algorithm. It consists of not only the output error but also the sum of all squared weights. With the new evaluation function, the learning algorithm minimizes not only output error but also weights. The value of parameter to balance effects of these two terms is decided actively during training of MLN. Next, to show the effectiveness of the proposed method, we apply it to pattern recognition problems. It is shown that the miss recognition rate and the activity of hidden units are improved.

An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits

This paper presents an enhanced iterative improvement method with multiple pins (EIIMP) to evaluate the maximum number of simultaneous switching gates. Although the iterative improvement method is a simple algorithm, it is powerful to this purpose. Keeping this advantage, we enhance it by two points. The first one is to change values for multiple successive primary inputs at a time. The second one is to rearrange primary inputs on the basis of the closeness that represents the number of overlapping gates between fan-out regions. Our method is shown to be effective by experiments for ISCAS benchmark circuits.

A genetic approach to test generation for logic circuits

This paper presents a genetic algorithm to generate tests for logic circuits. Bit strings corresponding to primary input patterns are evolved into tests for detecting a target fault by genetic operations. Some new techniques, such as a crossover operation based on fault-excitability and fault-drivability, are introduced to achieve high fault coverage. Experimental results show that the genetic approach is effective for solving test generation problem.<<ETX>>

Effect of regularization term upon fault tolerant training

To enhance fault tolerance of multi-layer neural networks, we proposed PAWMA (partially adaptive weight minimization approach). This method minimizes not only output error but also the sum of squares of weights (the regularization term). This method aims to decrease the number of connections whose faults strongly degrade the performance of MLNs (important connections). On the other hand, weight decay, which aims to eliminate unimportant connections, is base on the same idea. This method expects to keeping important connections and decaying unimportant connections. In this paper, we discuss about the contradiction between two effects of the regularization term. Through some experiment, we show that the difference between two effects is brought by the partially application of the regularization term.

Evaluation function for fault tolerant multi-layer neural networks

We propose a new learning algorithm to enhance fault tolerance of multilayer neural networks (MLN). This method is based on the idea that strong weights make MLN sensitive to faults. The purpose of the proposed algorithm is to make weights as small as possible through its training. The evaluation function of the proposed algorithm consists of not only the output error but also the square sum of weights. With the new evaluation function the learning algorithm minimizes not only output error but also weights. We discussed about the value of parameter to balance effects of these two terms. Next, we apply it to pattern recognition problems. As a result, it is shown that the degradation of recognition ratio is improved.

A method for evaluating upper bound of simultaneous switching gates using circuit partition

This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. In order to increase the accuracy, we adopted an evaluation function that takes account of both the interconnections among subcircuits and the number of generated subcircuits. Experimental results for ISCAS circuits show that the method efficiently evaluates the upper bounds of switching gates.

Parallel core testing with multiple scan chains by test vector overlapping

This paper proposes the parallel testing of cores with multiple scan chains using the test vector overlapping for reduction of SoC testing cost. Unlike conventional scan architecture for SoC testing, by introducing multiple scan chain cores, our method can reduce the test application time without increasing the number of I/O pins used in testing, and reduce the test data volume. A controller design and a new overlapping algorithm are also presented for the test vector overlapping with multiple scan chain cores. Experimental results show its effectiveness.

On test data compression using selective don't-care identification

This paper proposes an effective method for reducing test data volume under multiple scan chain designs. The proposed method is based on reduction of distinct scan vectors using selective don’t-care identification. Selective don’t-care identification is repeatedly executed under condition that each bit of frequent scan vectors is fixed to binary values (0 or 1). Besides, a code extension technique is adopted for improving compression efficiency with keeping decompressor circuits simple in the manner that the code length for infrequent scan vectors is designed as double of that for frequent ones. The effectiveness of the proposed method is shown through experiments for ISCAS’89 and ITC’99 benchmark circuits.