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Featured researches published by Hidehiko Sanada.


international conference on communications | 1988

Performance of window flow control scheme for interconnected packet networks

Miki Yamamoto; Ichiro Akiyoshi; Hikaru Nakanishi; Hidehiko Sanada; Yoshikazu Tezuka

When communication packet networks are interconnected, all internetwork traffic concentrates at the connecting point, and flow control is needed. X.75 provides window flow control at the connecting point (signaling terminal equipment). The authors investigate the performance of the window-flow-control scheme by simulation. They compare three ways of instituting flow-control-boundary division, and show that end-to-end within each network and between the two terminal is the best boundary division because its offers has satisfactory total delay with small buffer in the signaling terminal equipment. The concept and design of a service access procedure are presented for establishing transparent and reliable connections between the top three layer protocols of the ISO Open System Interconnection (OSI) and the corresponding bottom four layer protocols. The transport and network protocols have been selected to be the US Department of Defense standard transmission control protocol (IP), respectively. The upper layer protocols are made a part of the host processors software whereas the TCP/IP and the subsequent lower layer protocols are resident in a physically distinct device such as an interface unit.<<ETX>>


international conference on pattern recognition | 1988

A data structure suitable for representing the calligraphic rules for Chinese character evaluation

Jianchao Zeng; Takeshi Inoue; Hidehiko Sanada; Yoshikazu Tezuka

A data structure is proposed which is suitable for calligraphic rules (CRs) for the evaluation of brush-written Chinese characters (CCs). The data structure is based on a character model which generates CCs with a computer. Experiments have shown the representation of CRs and the evaluation of CCs can be realized, if the data structure is used which reflects the specific hierarchical relations among radicals and strokes.<<ETX>>


Systems and Computers in Japan | 1988

Simulation language based on logic for queueing network using time object

Takashi Watanabe; Hikaru Nakanishi; Hidehiko Sanada; Yoshikazu Tezuka

Queueing network simulation (QNS) has recently been considered as one of the important means for performance evaluation of the network-structured system. Presently, FORTRAN, simulation language GPSS and other languages are used to describe QNS softwares, but their describability is not very high. This paper notes that the simulation condition defining the QNS model can be described primarily by conditional form, and the logical language PROLOG has a high describability. A QNS-dedicated logical language SILQ (Simulation Language based on Logic for Queueing network), is proposed where QNS model is defined by Prolog form. The language has a feature that the program can be constructed without considering a Prolog algorithm, while it has the disadvantage that the time-scale, which is indispensable in a simulation, cannot be represented. As a means to introduce the time-scale without degrading the describability, a time object is proposed which provides a parameter representation for the state transition in the system. Then the programming primitives are prepared to describe the operation and other events for each time object in Prolog form. Programming examples by SILQ are presented, and the result is compared with other languages, indicating the high describability of the proposed language. A sequential processing system is constructed for SILQ, and a parallel processing system is discussed, aiming at the improvement of the processing speed.


Systems and Computers in Japan | 1987

D‐SSQ: A queueing network simulator with parallel execution control

Kei Sato; Hikaru Nakanishi; Hidehiko Sanada; Yoshikazu Tezuka

This paper discusses a node-distributed parallel-processing event-driven queueing network simulator, called D-SSQ. It employs the advanced execution control, aiming at the effective utilization of the parallelism inherent in the queueing network. The advanced control works as follows. Each processor first works ignoring the restrictions from other processors. If a contradiction is detected by manifesting the effects of other processors through the interprocessor communication, the contradiction is dissolved by partially cancelling the results of the previous processing. The processing performance of D-SSQ was examined by an experimental system and by the simulation using a large-scale computer. It is observed that the processing capability increases linearly with the number of processors, but does not increase as rapidly as was expected because of the large overhead in the distribution and the ineffective processing by the excessive advance control. Consequently, a restricted advance control has been considered, aiming at the elimination of the excessive advanced operation. It is indicated that the processing performance can be improved and there exists an optimum value for the extent of advanced operation.


Systems and Computers in Japan | 1987

Performance evaluation of asynchronous distributed processing system with limited‐advance processing

Takashi Watanabe; Hikaru Nakanishi; Hidehiko Sanada; Yoshikazu Tezuka

The traditional parallel processing assumes synchronous jobs, for which the processing can easily be planned before execution. On the other hand, the parallel processing is not usually considered for asynchronous jobs of a stochastic nature, such as the queueing network simulation, since the synchronization control of the processors is a problem. The advance processing has already been proposed as a control scheme for the processors in the asynchronous job parallel processing system. In this scheme, each processor performs the processing, thereby ignoring its relation to other processors. Thus the result of the processing is cancelled when a contradiction is found. Unfortunately, the processor may be too advanced in the execution, which results in a large number of cancelling, thus decreasing the processing ability per processor. From such a viewpoint, this paper discusses the limited-advance processing which is the improved scheme of advance processing. In this scheme, if the processor performs a certain amount of processing, it judges itself as too advanced, and awaits the progress of other processors. It is shown that there exists the optimum advance limit in this scheme, which is a function of the number of processors. The proposed scheme is analyzed to predict the optimum advance limit. In the analysis, the relation between the simulation time and the real time is specified, and the distribution overhead, cancelling time and the number of iterations are discussed. Comparing the result of numerical computation in the analysis and the result of measurement in the prototype system, the validity of the analysis is verified.


Systems and Computers in Japan | 1986

Delay Analysis of Wait System Model for Window-Controlled Packet Network and Optimal Window Allocation

Hiroshi Suzuki; Hikaru Nakanishi; Hidehiko Sanada; Yoshikazu Tezuka; Ichiro Akiyoshi

Window allocation is an important problem in designing a window-controlled packet network. Most of the early studies on this topic deal with the loss system model because of its analytical simplicity. In actual packet switched networks the admission delay of an input-regulated packet has to be considered and hence its wait system model need be studied. This paper presents delay analysis of the wait system model for a multilogic channel network (multi-LC model) with each logic channel having its own window. First, the equivalent flow method is validated in a single-LC model. Then, based on this method, an approximate approach applicable to the multi-LC model is developed. Our approximate method is evaluated in comparison with simulation results. Then, using this approximate method, the optimal window allocation problem is studied in a general wait system packet network. We obtain an interesting result showing that the optimal allocation with minimum delay can be achieved by equalizing the input regulation degree on each LC.


Electronics and Communications in Japan Part I-communications | 1989

Performance evaluation and optimization of ALOHA scheme with capture effect

Rongping Du; Hikaru Nakanishi; Yoshikazu Tezuka; Hiromi Okada; Hidehiko Sanada


Archive | 1990

A COMPUTER GENERATION MODEL OF BRUSH-USED HANDWRITTEN CHINESE CHARACTERS AND ITS APPLICATION IN EDUCATION

Jianchao Zeng; Xianrong Zhang; Takeshi Inoue; Hidehiko Sanada; Yoshikazu Tezuka


Archive | 1986

KNOWLEDGE BASED SOFTWARE DEVELOPMENT SUPPORT SYSTEM FOR QUEUEING NETWORK SIMULATION.

Hiroyuki Yamada; Takahira Yamaguchi; Hidehiko Sanada; Osamu Kakusho; Yoshikazu Tezuka


international conference on communications | 1986

Delay Analysis of Window Controlled Network with Finite Input Buffer.

Miki Yamamoto; Hikaru Nakanishi; Hidehiko Sanada; Yoshikazu Tezuka; Ichiro Akiyoshi

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Takeshi Inoue

Toyohashi University of Technology

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