Hidehiro Watanabe

A 0.67 /spl mu/m/sup 2/ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs

An ultra high-density NAND-structured memory cell, using a new Self-Aligned Shallow Trench Isolation (SA-STI) technology, has been developed for a high performance and low bit cost 256 Mbit flash EEPROM. The SA-STI technology results in an extremely small cell size of 0.67 /spl mu/m/sup 2/ per bit, 67% of the smallest flash memory cell reported so far, by using a 0.35 /spl mu/m technology. The key technologies to realize a small cell size are (1) 0.4 um width Shallow Trench Isolation (STI) to isolate neighboring bits and (2) a floating gate that is self-aligned with the STI, eliminating the floating-gate wings. Even though the floating-gate wings are eliminated, a high coupling ratio of 0.65 can be obtained by using the side-walls of the floating gate to increase the coupling ratio. Using this self-aligned structure. A reliable tunnel oxide can be obtained because the floating gate does not overlap the trench corners, so enhanced tunneling at the trench corner is avoided. Therefore, the SA-STI cell combines a low bit cost with a high performance and a high reliability, such as the fast programming (0.2 /spl mu/sec/byte), fast erasing (2 msec), good write/erase endurance (>10/sup 6/ cycles), and excellent read disturb characteristics(>10 years). This paper describes the process technologies and the device performance of the SA-STI cell, which can be used to realize NAND EEPROMs of 256 Mbit and beyond.<<ETX>>

Stacked capacitor cells for high-density dynamic RAMs

A novel process sequence fabricating stacked capacitor cells has been developed for high-density dynamic RAMs (random access memories). Enhanced cell capacitance can be obtained by opening the contact window for the lower electrode of the stacked capacitor after the deposition of the electrode poly-Si. This is followed by additional substrate Si etching. The procedure results in sufficient cell capacitance even in 64-Mb dynamic RAMs.<<ETX>>

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

The dependence of MOSFET gate controllability on the field-isolation scheme is investigated using three-dimensional simulation. It is found that a fully-recessed-oxide (trench) isolated MOSFET has a steep subthreshold characteristic and high transconductance in comparison with a nonrecessed device. These features result from the small depletion capacitance due to the crowding of the gates fringing field at the channel edge. It is also found that the gate and diffused line capacitances in the case of fully-recessed-oxide isolation are small, so that high switching speed operation can be expected. These features are enhanced with a reduction in the channel width, especially for lower-submicrometer-width MOSFETs. A drawback of a fully-recessed-oxide MOSFETs is its low threshold voltage. However, the leakage current is not as large as that inferred from the inverse narrow-channel effect because of its steep subthreshold characteristic. Several countermeasures for this low threshold voltage are discussed. >

Human brain glucose metabolism mapping using multislice 2D 1H‐13C correlation HSQC spectroscopy

A method for multivolume 2D 1H‐13C correlation spectroscopy, multislice heteronuclear single quantum coherence (HSQC), is proposed. This permits human brain metabolism from glucose to amino acids to be followed using a 2‐T whole‐body scanner. The modifications from the conventional HSQC are that the 180°(13C) and 180°(1H) pulses are separated in time in the preparation period and that the 180°(13C) pulse is applied at 1/(4JCH) before the 90°(1H) polarization transfer (PT) pulse. The preparation (echo) time can be set longer than 1/(2JCH) so that, even in a whole‐body system, slice‐selective pulses and gradients can be applied. Another modification is that the 90°(1H) reverse PT pulses after the creation of 2IzSz are used as multislice pulses. The time‐course of glutamate C4 could be followed with 15‐min temporal resolution from the HSQC spectra obtained from the brains of volunteers after the oral administration of glucose C1, and the maximum S/N was 3. Magn Reson Med 43:525–533, 2000.

3D localized 1H-13C heteronuclear single-quantum coherence correlation spectroscopy in vivo

A method for spatially three‐dimensional (3D) localized two‐dimensional (2D) 1H‐13C correlation spectroscopy, localized HSQC, is proposed. This method has the following special feature in the preparation period. The 180°(13C) and 180°(1H) pulses are separated in time, and the 180°(13C) pulse is applied at 1/(4 1JCH) before the 90°(1H) polarization transfer pulse. The preparation (echo) period 2τ can then be set substantially longer than 1/(2 1JCH), so that even in a whole‐body system, slice‐selective 90°(1H) pulses and gradient pulses can be applied in that period. The localization capabilities of this method were confirmed in a phantom experiment. The 3D localized 2D 1H‐13C correlation spectra from a monkey brain in vivo were obtained after [1‐13C]glucose injection, and amino acid metabolism was detected; that is, [4‐13C]glutamate appeared immediately after the injection, followed by the appearance of [2‐13C]glutamate, [3‐13C]glutamate, and [4‐13C]glutamine. Magn Reson Med 43:200–210, 2000.

A novel side-wall transfer-transistor cell (SWATT cell) for multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (Vth) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide Vth is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the Vth of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the Vth distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell realizes a very small cell size of 0.67 /spl mu/m/sup 2/ for a 0.35 /spl mu/m rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROMs of 512 Mbit and beyond.

Corner-rounded shallow trench isolation technology to reduce the stress-induced tunnel oxide leakage current for highly reliable flash memories

This paper describes the key technology to realize highly reliable flash memory cells, which have submicron Shallow Trench Isolation (STI). It has been clarified for the first time that the Stress-Induced Leakage Current (SILC) of the tunnel oxide on the rounded corners of the STI edges is about one order smaller than SILC of the flat oxide. Moreover, data retention characteristics of the flash memory cells with the rounded corners are drastically improved due to the reduction of SILC. Therefore, corner-rounded STI technology will surely become necessary for highly reliable quarter-micron flash memories and beyond.

New effects of trench isolated transistor using side-wall gates

In order to realize a high performance switching transistor, a new trench isolated transistor with side-wall gates has been developed. In this transistor with a triple-gate structure, the side-wall of the trench is used as an extra-channel region. The new effects of trench isolated transistor with a triple-gate structure have been described. The advantages of this transistor are excellent cutoff characteristics, a small substrate bias effect and high reliability characteristics. It is found that the side-wall gate along the channel edge plays an important role for increasing the gate controllability and for decreasing the concentration of the electric field at the drain.

In vivo Investigation of Glutamate–Glutamine Metabolism in Hyperammonemic Monkey Brain Using 13C-Magnetic Resonance Spectroscopy

To investigate the metabolism of glutamate and glutamine in living monkey brain, a system of in vivo 13C magnetic resonance spectroscopy (MRS) using 1H-decoupled 13C spectroscopy combined with monitoring temperature changes in the brain by MR phase mapping was developed. Serial 13C-NMR spectra of the amino acids glutamate and glutamine were acquired non-invasively over 4 h from anesthetized monkey brain after the intravenous administration of [1-13C]glucose (0.5–1.0 g/kg). In the acute hyperammonemic state induced by the administration of ammonium acetate (77 mg/kg bolus), it was observed that 13C incorporation into glutamine-4 was clearly accelerated, without changes of 13C incorporation into glutamate-4. During hyperammonemia, it was shown directly by [2-13C]glucose administration that the anaplerotic pathway for the TCA cycle was also augmented, contributing to the formation of glutamine in the astroglia.

Effects of a new trench-isolated transistor using sidewall gates

In this structure, the sidewall of the trench is used as an extra channel region. The sidewall gate electrode, which covers the sharp convex corner of the trench, increases the electric field at the channel edge. The advantages of this transistor are excellent cutoff characteristics, a small substrate bias effect, and high reliability (compared with the LOCOS-isolated transistor). The sidewall gate along the channel edge plays an important role in increasing gate controllability and decreasing the electric field at the drain. >