Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Katsuhiko Hieda is active.

Publication


Featured researches published by Katsuhiko Hieda.


IEEE Transactions on Electron Devices | 2000

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

Atsushi Yagishita; Tomohiro Saito; Kazuaki Nakajima; Seiji Inumiya; Yasushi Akasaka; Yoshio Ozawa; Katsuhiko Hieda; Yoshitaka Tsunashima; Kyoichi Suguro; Tsunetoshi Arikado; Katsuya Okumura

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.


Journal of the Optical Society of America | 1980

Use of a total absorption ATR method to measure complex refractive indices of metal-foils

Hiroe Kitajima; Katsuhiko Hieda; Yasuharu Suematsu

In this paper, the use of a total absorption attenuated total reflection (ATR) method to measure complex refractive indices and thicknesses of thin foils is discussed. Our studies show that in a prism metal-foil coupling system, the gap thickness between the prism and the metal-foil modifies the state of the coupled surface plasmons on the metal-foil interface, and yields total absorption at three different incident angles, under optimum conditions, respectively. The dependence of the conditions for total absorption on the complex refractive index and on the foil thickness is discussed. By preparing three prism coupling systems with different refractive indices, and by measuring the incident angle at minimum reflectance in each system, complex refractive indices and foil thicknesses of thin gold-foils have been measured.


Applied Optics | 1980

Thickness measurement of ultrathin films on metal substrates using ATR

Hiroe Kitajima; Katsuhiko Hieda; Yasuharu Suematsu

By modifying the surface plasma mode on a bare metal surface with an ultrathin film deposited on the metal, we measured the film thickness by attenuated total reflection (ATR). Various factors causing measurement errors are estimated with numerical examples. As a result, for example, it is shown that for some thicknesses, the errors due to the real part of the complex refractive index of a metal substrate become extremely small. Thicknesses of SiO(2) films sputtered onto Au foil and A1(2)O(3) films produced on Al foil by oxidation are measured.


Applied Optics | 1981

Optimum conditions in the attenuated total reflection technique

Hiroe Kitajima; Katsuhiko Hieda; Yasuharu Suematsu

In this paper the optimum condition for using the attenuated total reflection (ATR) technique is studied. In optimum conditions, the energy of an incident plane wave can be totally absorbed. The optimum condition can be realized by fabricating a localized thickness variation in the gap between a prism and a sample substrate with a point contact pressure. In the ATR technique, for example, the complex refractive index and the foil thickness of a thin metal foil, and the gap thickness are unknown parameters. To determine these unknown parameters, we prepared three prism coupling systems with different refractive indices. By this technique, we measured the complex refractive indices and the foil thicknesses of thin gold foils sputtered onto glass substrates, and the refractive index and the film thickness of a silica film sputtered onto a metal substrate.


Japanese Journal of Applied Physics | 2003

Control of Two Types of Dielectric Relaxation Current for Ta2O5 Metal-Insulator-Metal Capacitors

Masahiro Kiyotoshi; Katsuhiko Hieda; Yoshiaki Fukuzumi; Yusuke Kohyama; Toshiya Suzuki; Daisuke Matsunaga; Koichi Hashimoto

Ta2O5 is the most promising high-k dielectric candidate for metal-insulator-metal (MIM) capacitors, but its dielectric relaxation (DR) currents may cause irrecoverable charge loss, although DR is a universal phenomenon of normal dielectrics. Therefore, the Ta2O5 MIM capacitors DR chasracteristics and their control were investigated. Ta2O5 DR is composed of two components. One component shows t-1-type time decay, which is assumed to be caused by nonuniformity of electron polarization and is almost of the same order as that of SiN. Thus, its influence on dynamic random access memory (DRAM) operation will be limited. The other component shows t-0.5-type time decay, which is caused by hydrogen deoxidation of Ta2O5, and is dominant in the case of deoxidized Ta2O5 DR. It causes about 16% charge loss. Namely, it will have an adverse influence on DRAM operation. N2 annealing is a possible solution for the reduction of this t-0.5-type DR.


Japanese Journal of Applied Physics | 1999

Plasma-Damage-Free Gate Process Using Chemical Mechanical Polishing for 0.1 µm MOSFETs

Tomohiro Saito; Atsushi Yagishita; Seiji Inumiya; Kazuaki Nakajima; Yasushi Akasaka; Yoshio Ozawa; Hiroyuki Yano; Katsuhiko Hieda; Kyoichi Suguro; Tsunetoshi Arikado; Katsuya Okumura

We propose a new transistor process called the Damascene gate process, where in a gate electrode is patterned by chemical mechanical polishing (CMP). In this process, source/drain implants are carried out by using a dummy gate pattern as a mask and activation annealing is completed before the actual gate oxide formation. After removal of the dummy gate, fresh oxide and gate electrode films are formed in grooves and the gate electrode film is patterned by CMP. As a result, the gate electrode surface is completely planarized and the sheet resistivity of the gate electrode is very uniform in a line width range from 0.2 µm to 5 µm. Metal-oxide-semiconductor-field-effect-transistors (MOSFETs) formed by the Damascene gate process were found to show higher electron mobility, smaller threshold voltage deviation and lower subthreshold swing due to lower surface state density as compared with conventional transistors. Therefore, the Damascene gate process is promising for the fabrication of sub-quarter-micron MOSFETs.


Japanese Journal of Applied Physics | 1981

Various Light Resonance Mechanisms in Dielectric and Metallic Layers, and a Measurement Procedure for Optical Constants

Hiroe Kitajima; Katsuhiko Hieda; Yasuharu Suematsu

In this paper, various light resonance mechanisms in dielectric and metallic film layers have been studied. In a prism metal film coupling structure for surface plasma wave excitations, under optimum conditions, which are related to the thickness of the metal film and the gap between the prism and the metal film, the reflectance at the prism gap boundary becomes zero at three different angles of incidence. Furthermore, anomalous light absorption occurs due to the excitation of longitudinal plasma waves; even when the collison loss of the free electrons is assumed to be zero, the reflectance becomes zero. A measurement procedure is also shown with experimental data for determining the complex refractive index and the film thickness of metal films at the same time.


Archive | 2005

IMMERSION TYPE EXPOSURE DEVICE

Katsuhiko Hieda; 克彦 稗田


Archive | 1999

Etching method, chemical vapor deposition apparatus, cleaning method thereof and quartz member therefor

Kazuhiro Eguchi; Katsuhiko Hieda; Masahiro Kiyotoshi; Katsuya Okumura; Soichi Yamazaki; 勝弥 奥村; 壮一 山崎; 和弘 江口; 正弘 清利; 克彦 稗田


Archive | 2005

METHOD FOR FORMING PHOTORESIST PATTERN, AND SUBSTRATE FOR FORMING THE PHOTORESIST PATTERN

Katsuhiko Hieda; 克彦 稗田

Collaboration


Dive into the Katsuhiko Hieda's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar

Hiroe Kitajima

Kyushu Institute of Technology

View shared research outputs
Top Co-Authors

Avatar

Yasuharu Suematsu

Tokyo Institute of Technology

View shared research outputs
Researchain Logo
Decentralizing Knowledge