Hideki Kiritani

High thermal conductivity underfill for the thermal management of three-dimensional (3D) chip stacks

It has been experimentally clarified that one of the thermal resistance bottlenecks of a three-dimensional (3D) chip stack is interconnection (solder bumps and underfill) between stacked chips. High thermal conductivity underfill, which we call high thermal conductivity inter chip fill (ICF), is expected to reduce the thermal resistance of interconnection efficiently, because the area which is occupied by ICF is larger than solder bumps. It is shown by simulation how high thermal conductivity ICF contributes to decrease the thermal resistance of interconnection. Also material formulation of high thermal conductivity ICF is demonstrated.

Pre-Applied Inter Chip Fill for 3D-IC Chip Joining

For the conventional two dimensional (2D) packaging of integrated circuit (IC), reflow and capillary under fill have been used for more than a decade. But for the purpose of low power and high performance of IC, three dimensional IC (3D-IC) have been proposed in recent years. In case of 3D-IC, both bump pitches and gaps between stacked thin chips should be fine and narrow, so that pre-applied inter chip fill (ICF) which is applied in thermal compression bonding have been proposed. In this process, not only low viscosity but also thermal conductivity is simultaneously required. In this study, some of selected epoxy based matrix and filler were simulated and evaluated for pre-applied ICF, we confirmed its process applicability to pre-applied chip bonding. Physical characteristics of cured ICF and void-less joining were also discussed.