Hideki Yoshizawa

3D graphics processor chip set

Increasingly, 3D graphics is becoming the rule rather than the exception in applications such as games, CAD/CAM, and video production. Some LSIs provide rendering capabilities, but require an additional CPU to perform essential geometry transformations. Fujitsus chip set solves that problem using two processors to render 300,000 polygons per second (for flat-shaded triangles with texture)-performance comparable to that of advanced game machines.Our three-dimensional graphics processor chip set contains a geometric conversion processor (TGPx4) and a rendering processor (AGP). In the minimum configuration (one TGPx4 and one AGP), this chip ...

Cluster architecture for reconfigurable signal processing engine for wireless communication

We describe a dynamic reconfigurable baseband signal-processing engine suitable for mobile communications that require short operation latency. Signals are processed using a cluster group, which consists of clusters containing heterogenous processor elements (PEs), inter-PE networks, and a sequencer that controls dynamic reconfiguration. The cluster group also has dedicated shared signal processing resources. In the cluster, combined data transfer and operations are carried out within one cycle to minimize operation latency, except for the multicycled PE. We evaluated the architecture by mapping several physical-layer IEEE802.11a and 11b wireless LAN algorithms. The results confirmed a shorter processing latency.

Flexible Signal Processing Platform Chip for Software Defined Radio with 103 GOPS Dynamic Reconf1gurable Logic Cores

Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip baseband processing LSI for SDR based on a hybrid architecture of coarse-grain reconfigurable logic cores and flexible accelerator modules to achieve the required features. The maximum performance is 103 GOPS. Moreover, we implemented IEEE 802.11a and IEEE 802.11b, and show the effectiveness in latency.

Cyclic reconfiguration for pipelined applications on coarse-grain reconfigurable circuits

A new reconfiguration technique for pipelined applications on coarse-grain reconfigurable circuits, the cyclic reconfiguration method, is proposed. In this method, the configurations that have interleaved pipeline stages are switched once per clock. This method improves the ratio of effective processing elements in one configuration plane, and the number of switching configuration planes is reduced. As a result, throughput is improved. In comparison with a FIR filter, throughput by the cyclic reconfiguration method is two times the throughput of the previously introduced incremental reconfiguration method.