Hisanori Fujisawa

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned.<<ETX>>

Variable ordering algorithms for ordered binary decision diagrams and their evaluation

Ordered binary decision diagrams (OBDDs) use restricted decision trees with shared subgraphs. The ordering of variables is fixed throughout an OBDD diagram. However, the size of an OBDD is very sensitive to variable ordering, especially for large circuits. The results of experiments in variable ordering using an experimentally practical algorithm are presented. The algorithm is basically a depth-first traversal through a circuit from the output to the inputs. With this algorithm, circuits having more than 3000 gates and more than 100 inputs can be expressed in reasonable CPU time and with practical memory requirements. >

Cluster architecture for reconfigurable signal processing engine for wireless communication

We describe a dynamic reconfigurable baseband signal-processing engine suitable for mobile communications that require short operation latency. Signals are processed using a cluster group, which consists of clusters containing heterogenous processor elements (PEs), inter-PE networks, and a sequencer that controls dynamic reconfiguration. The cluster group also has dedicated shared signal processing resources. In the cluster, combined data transfer and operations are carried out within one cycle to minimize operation latency, except for the multicycled PE. We evaluated the architecture by mapping several physical-layer IEEE802.11a and 11b wireless LAN algorithms. The results confirmed a shorter processing latency.

Flexible Signal Processing Platform Chip for Software Defined Radio with 103 GOPS Dynamic Reconf1gurable Logic Cores

Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip baseband processing LSI for SDR based on a hybrid architecture of coarse-grain reconfigurable logic cores and flexible accelerator modules to achieve the required features. The maximum performance is 103 GOPS. Moreover, we implemented IEEE 802.11a and IEEE 802.11b, and show the effectiveness in latency.

A WiMAX turbo decoder with tailbiting BIP architecture

A tailbiting block-interleaved pipelining (TB-BIP) is proposed for deeply-pipelined turbo decoders. Conventional sliding window block-interleaved pipelining (SW-BIP) turbo decoders suffer from many warm-up calculations when the number of pipeline stages is increased. However, by using TB-BIP, more than 50% of the warm-up calculations are reduced as compared to SW-BIP. We have implemented a TB-BIP WiMAX turbo decoder with four pipeline stages in the area of 3.8 mm2 using a 0.18 µm CMOS technology. The chip achieved 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

A precise event-driven circuit simulator based on predicted fan-in voltages

We propose a new event-driven circuit simulation method for MOS transistor circuits. This method is based on predicted and revised voltages of nodes, and is highly accurate. Furthermore this method can use an effective block selection function (EBSF) which allows faster simulation with the same accuracy. In industrial circuits, actually our method achieved accuracy equal to or higher than that of a SPICE-like simulator at 3 to 5 times the speed without EBSF, or 11 to 22 times the speed with EBSF.<<ETX>>

Voltage droop reduction for multiple-power domain SoCs with on-die LDO using output voltage boost and adaptive response scaling

Low power techniques such as clock gating and dynamic frequency scaling cause a sudden surge in power supply current. To reduce the voltage droop induced by such a surge in the load current of an LDO regulator, we propose output voltage boost and adaptive response scaling techniques that utilize clock activation detection. Measured results from a test chip fabricated in 65-nm CMOS technology show that a combination of the two techniques reduces the worst-case output voltage droop by 63% compared to operation without them. This results in a voltage offset reduction from 45% to 15%, which leads to 20% power savings.

Cyclic reconfiguration for pipelined applications on coarse-grain reconfigurable circuits

A new reconfiguration technique for pipelined applications on coarse-grain reconfigurable circuits, the cyclic reconfiguration method, is proposed. In this method, the configurations that have interleaved pipeline stages are switched once per clock. This method improves the ratio of effective processing elements in one configuration plane, and the number of switching configuration planes is reduced. As a result, throughput is improved. In comparison with a FIR filter, throughput by the cyclic reconfiguration method is two times the throughput of the previously introduced incremental reconfiguration method.