Hidemasa Kubota

Generalized method of the time-domain circuit simulation based on LIM with MNA formulation

In this paper, we show the generalized method of the time-domain circuit simulation based on LIM. First, the formulation of the circuit for LIM is modified and generalized. Furthermore, the modified simulation algorithm is suggested. As a result, our method is applicable to any structure of circuits. Some example circuits are simulated and the proposed method is compared with the conventional ones, in order to show the validity and efficiency of our method

Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation

A fast method for timing analysis of large scale RLC networks using the RLCG-MNA formulation, which provides good properties for fast matrix solvers, is presented. The proposed method is faster than INDUCTWISE and more general than the RLP algorithm, where INDUCTWISE and RLP algorithm are known as the state-of-art simulation methods. In the numerical example, good performances of the proposed method are illustrated compared with the previous works

Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters

In this paper, we focus on the verification of the PCB/package power integrity, which becomes very important for the design of state-of-art high speed digital circuits. The simulation of power distribution networks (PDNs) of the PCB/package, which can be modeled as a large number of RLC lumped components, is a time-consuming task for using the conventional circuit simulator, such as SPICE. For this problem, we propose a parallel-distributed time-domain circuit simulation algorithm based on LIM. Furthermore, an effective modeling of frequency-dependencies of the PDNs, such as skin effects and dielectric losses, to solve by LIM is proposed

Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm

This paper presents a fast transient simulation method for power distribution networks (PDNs) of the PCB/Package. Because these PDNs are modeled as large-scale linear circuits consisting of a large number of RLC elements, it takes large costs to solve by conventional circuit simulators, such as SPICE. Our simulation method is based on the leapfrog algorithm, and can solve RLC circuits of PDNs faster than SPICE. Actual PDNs have frequency-dependent dispersions such as the skin-effect of conductors and the dielectric loss. To model these dispersions, more number of RLC elements are required, and circuit structures of these dispersion models are hard to solve by using the leapfrog algorithm. This paper shows that the circuit structures of dispersion models can be converted to suitable structures for the leapfrog algorithm. Further, in order to reduce the simulation time, our proposed method exploits parallel computation techniques. Numerical results show that our proposed method using single processing element (PE) enables a speedup of 20--100 times and 10 times compared to HSPICE and INDUCTWISE with the same level of accuracy, respectively. In a large-scale example with frequency-dependent dispersions, our method achieves over 94% parallel efficiency with 5PEs.

What-if analyses of multi-layer PWB embedded in the digital still camera with parallel-distributed FDTD-based simulator "BLESS"

This paper describes a full-wave EMI (electromagnetic interference) simulator BLESS (Board Layout Evaluation and Suggestion System) for the printed wiring board (PWB) design with the consideration of electromagnetic compatibility (EMC) and power/signal integrity. This simulator is based on the parallel-distributed finite-difference time-domain (FDTD) method, and works on a PC-cluster. The accuracy of analysis by BLESS is verified in comparison with s-parameter measurements. Using the simulator, the full-wave analysis of the multi-layer PWB in a commercial digital still camera is demonstrated. With the aid of what-if analysis results, PWB design can be verified and optimized with less number of trial productions.

Analysis of power/ground planes by PCB simulator with model order reduction technique

With the progress of integration of circuits and PCBs (printed circuit boards), novel techniques have been required for verification of signal integrity. Noise analysis of the power/ground planes is one of the most important issues. This paper describes a high-speed simulator for PCBs which contain interconnects with nonlinear terminations. This simulator is based on the ASSIST environmental tool constructed for development of the circuit simulators, and is combined with PRIMA (passive reduced-order interconnect macromodeling algorithm). In this simulator, an efficient implementation of PRIMA is considered with use of a voltage-controlled current source (VCCS) model. Finally, this simulator is applied to the analysis of power/ground planes of simple PCBs, and the validity is verified.

Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation

One or 2-step Gauss-Jacobi method is efficiently incorporated to the large scale interconnect analysis. In order to make the Gauss-Jacobi method within 1 or 2 iterations during each time step, the interconnect network is formulated by the RLCG-MNA formulation. In the numerical example, it is illustrated that the one-step Gauss-Jacobi method is 1,035 times faster than Berkeley SPICE and several tens times faster than INDUCTWISE which is known as the recent fast simulation method. Further, we show that the 2-step Gauss-Jacobi method is rational from efficiency and accuracy points of views

Passive approximation of tabulated frequency-data by Fourier expansion method

The passive approximation of tabulated frequency-data for modeling package, PCB, and integrated circuits is presented. The macromodels in the Laplace-domain are directly obtained by the Fourier series approximation of the frequency-data and are represented using a Laguerre basis. The rigorous proof of passivity preservation associated with the proposed models is provided.

Hybrid reduction technique for efficient simulation of linear/nonlinear mixed circuits

In this paper, we propose a new method which makes transient simulation faster for the circuit including both nonlinear and linear elements. First, the method for generating the projection matrix with krylov-subspace technique is described. The order of the circuit equation is reduced by congruence transformation with the projection matrix. Next, we suggest a method which can calculate the reduced Jacobian matrix directly in the each Newton-Raphson iteration. Since this technique does not need to calculate the original size of Jacobian matrix, the calculation cost is reduced drastically. Therefore, efficient circuit simulation can be achieved. Finally, our method is applied to some example circuits: and the validity of the nonlinear circuit reduction technique is verified.

An Enhanced Time-Domain Circuit Simulation Technique Based on LIM

In this paper, we show the generalized method of the time-domain circuit simulation based on LIM. Our method is applicable to any structure of circuits by combination with the SPICE-like method. In order to show the validity and efficiency of our method, an example circuit is simulated and the proposed method is compared with the conventional ones.