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Dive into the research topics where Hidenobu Matsumura is active.

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Featured researches published by Hidenobu Matsumura.


european test symposium | 2016

An optical/electrical test system for 100Gb/s optical interconnection devices with high volume testing capability

Tasuku Fujibe; Kazuki Shirahata; Takeshi Mizushima; Hidenobu Matsumura; Daisuke Watanabe; Hiroyuki Mineo; Shin Masuda

100-Gb/s optical interconnection devices are expected to be deployed widely in large scale datacenters in the near future. As it is required to setup these large scale datacenters in a short period, 100-Gb/s devices need to have shorter time-to-market. We have developed a test system which is capable of testing 16-lanes of 28-Gb/s both optical and electrical interfaces simultaneously. This multiple lane configuration provides a more realistic operating environment to the device under test in order to confirm inter-lane interference or power integrity. The test system also includes repeatable optical connectors which has variation of insertion loss less than +/- 0.3dB after more than 100,000 repeated plug/unplug operations. This test solution can be applied to high speed optical interconnection device testing in high volume manufacturing.


asian test symposium | 2016

An Optical Interconnection Test Method Applicable to 100-Gb/s Transceivers Using an ATE Based Hardware

Kazuki Shirahata; Takeshi Mizushima; Tasuku Fujibe; Hidenobu Matsumura; Tomoyuki Itakura; Masahiro Ishida; Daisuke Watanabe; Shin Masuda

Drastically increasing network traffic within datacenters requires high volume manufacturing for 100-Gb/s optical transceivers. This paper proposes high throughput test method for optical transceivers using Automated Test Equipment (ATE) with both optical and electrical frontend. By using proposed solution, 4.4 times higher throughput can be achieved.


asian test symposium | 2016

An Optical/Electrical Test System for 100-Gb/s Optical Interconnection Devices for High Volume Production

Takeshi Mizushima; Kazuki Shirahata; Tasuku Fujibe; Hidenobu Matsumura; Daisuke Watanabe; Hiroyuki Mineo; Shin Masuda

100-Gb/s optical interconnection devices are expected to be deployed widely in large scale datacenters. In order to improve the productivity of these optical devices, this paper proposes a test solution equipped with 16-lanes of 28-Gb/s both optical and electrical interfaces. In addition to these high-speed ports to test the devices, the test solution also includes device fixture technology which provides stable and repeatable insertion loss for more than 100,000 repeated plug/unplug operations. This test solution can be applied to high speed optical interconnection device testing in high volume manufacturing.


Archive | 1998

Semiconductor integrated circuit evaluation system

Koji Takahashi; Hiroaki Yamoto; Hidenobu Matsumura


Archive | 1998

Semiconductor integrated circuit design and evaluation system using cycle base timing

Hidenobu Matsumura; Hiroaki Yamoto; Koji Takahashi


Archive | 1998

High speed test pattern evaluation apparatus

Hidenobu Matsumura; Hiroaki Yamoto; Koji Takahashi


Archive | 2010

RECEIVING APPARATUS, TEST APPARATUS, RECEIVING METHOD, AND TEST METHOD

Shusuke Kantake; Hidenobu Matsumura


Archive | 1999

Semiconductor integrated circuit design verification system

Hidenobu Matsumura; Koji Takahashi; Hiroaki Yamoto; 英宜 松村; 裕明 矢元; 公二 高橋


Archive | 2009

Receiving apparatus, testing apparatus, receiving method and testing method

Shusuke Kantake; 秀介 寒竹; Hidenobu Matsumura; 英宜 松村


Archive | 2005

Semiconductor device, test apparatus and measurement method therefor

Makoto Yamazaki; Hidenobu Matsumura; Yasuo Furukawa

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