Tasuku Fujibe

Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing

A dynamic arbitrary jitter injection method that can be integrated into our high speed and high density CMOS timing generator has been developed. This method makes it possible to inject arbitrary jitter including Periodic Jitter, Random Jitter and Data Dependent Jitter in order to realize flexible SerDes device testing. By this method, furthermore, jitter injection is dynamically and synchronously controllable according to a test pattern. We have implemented our jitter injection method in a prototype chip to demonstrate the concept. The chip includes a 6.5Gb/s timing generator and was fabricated by a 90nm CMOS process. Area and power consumption for each edge including the jitter injection scheme and timing generator are 0.2mm2 and 43.8mW respectively.

8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability

In this paper, we present a small sized CMOS pin-electronics hardware macro applicable to 8Gbps real-time functional testing. The macro includes a driver, comparators, DACs, and control logic embedded within an area of size 2mm × 1.6mm. As the macro is implemented on a 65nm standard CMOS process, it can be implemented together with pattern generators and timing generators to realize a single chip pin electronics solution. Moreover, the macro is capable of simultaneous bi-directional (SBD) signaling, which greatly reduces test time. A simple and reliable method to evaluate SBD is also discussed. We have applied our macro to a test chip to prove that the macro is applicable to an 8Gbps test system.

An optical/electrical test system for 100Gb/s optical interconnection devices with high volume testing capability

100-Gb/s optical interconnection devices are expected to be deployed widely in large scale datacenters in the near future. As it is required to setup these large scale datacenters in a short period, 100-Gb/s devices need to have shorter time-to-market. We have developed a test system which is capable of testing 16-lanes of 28-Gb/s both optical and electrical interfaces simultaneously. This multiple lane configuration provides a more realistic operating environment to the device under test in order to confirm inter-lane interference or power integrity. The test system also includes repeatable optical connectors which has variation of insertion loss less than +/- 0.3dB after more than 100,000 repeated plug/unplug operations. This test solution can be applied to high speed optical interconnection device testing in high volume manufacturing.

An Optical Interconnection Test Method Applicable to 100-Gb/s Transceivers Using an ATE Based Hardware

Drastically increasing network traffic within datacenters requires high volume manufacturing for 100-Gb/s optical transceivers. This paper proposes high throughput test method for optical transceivers using Automated Test Equipment (ATE) with both optical and electrical frontend. By using proposed solution, 4.4 times higher throughput can be achieved.

An Optical/Electrical Test System for 100-Gb/s Optical Interconnection Devices for High Volume Production

100-Gb/s optical interconnection devices are expected to be deployed widely in large scale datacenters. In order to improve the productivity of these optical devices, this paper proposes a test solution equipped with 16-lanes of 28-Gb/s both optical and electrical interfaces. In addition to these high-speed ports to test the devices, the test solution also includes device fixture technology which provides stable and repeatable insertion loss for more than 100,000 repeated plug/unplug operations. This test solution can be applied to high speed optical interconnection device testing in high volume manufacturing.

Real-Time Testing Method for Multilevel Signal Interfaces and Its Impact on Test Cost

This paper proposes a real-time testing method for multilevel signal interfaces. It utilizes multilevel drivers that can modulate both the voltage and timing of an output signal, and multilevel comparators based on a dynamic threshold concept. The authors also consider the impact on test cost of the proposed system and compares that cost with a conventional binary test system.