Hidenori Kitai

Analysis of Gate Oxide Nitridation Effect on SiC MOSFETs by Using Hall Measurement and Split C–V Measurement

In this study, 4H–SiC inversion layers were experimentally evaluated by Hall and split C–V measurements, and scattering mechanisms related to gate oxide nitridation were analyzed. Three typical samples with different crystal plane directions and gate oxidation conditions were prepared, and their total trap density and Hall mobility were compared. Based on the temperature dependence of the Hall mobility, we found that scattering mechanisms differed for each sample. The sample C-face oxynitride which had a high nitrogen density at the metal–oxide–semiconductor (MOS) interface, showed a similar temperature dependency to that of ionized impurity scattering. This result suggests that high-density nitrogen acts as donors that supply free carriers and cause ionized impurity scattering, just like in a bulk crystal. In addition, the sample C-face wet has lowest influence of the Coulomb scattering because of the lowest temperature dependence of Hall mobility and the lowest total trap density.

Electrical and physical characterizations of the effects of oxynitridation and wet oxidation at the interface of SiO2/4H-SiC(0001) and

The effects of oxynitridation and wet oxidation at the interface of SiO2/4H-SiC(0001) and were investigated using both electrical and physical characterization methods. Hall measurements and split capacitance–voltage (C–V) measurements revealed that the difference in field-effect mobility between wet oxide and dry oxynitride interfaces was mainly attributed to the ratio of the mobile electron density to the total induced electron density. The surface states close to the conduction band edge causing a significant trapping of inversion carriers were also evaluated. High-resolution Rutherford backscattering spectroscopy (HR-RBS) analysis and high-resolution elastic recoil detection analysis (HR-ERDA) were employed to show the nanometer-scale compositional profile of the SiC-MOS interfaces for the first time. These analyses, together with cathode luminescence (CL) spectroscopy and transmission electron microscopy (TEM), suggested that the deviations of stoichiometry and roughness at the interface defined the effects of oxynitridation and wet oxidation at the interface of SiO2/4H-SiC(0001) and .

Development of a novel 1200-V-class 4H-SiC implantation-and-epitaxial trench MOSFET with low on-resistance

In this paper, we present a newly developed 1200-V-class 4H-SiC implantation-and-epitaxial trench metal–oxide–semiconductor field-effect transistor (IETMOSFET). It uses high-quality p- and n-epitaxial layers for a channel and a trench current spreading layer (TCSL), respectively. It can enhance both channel mobility and bulk mobility for current spreading by avoiding damage and impurity variations caused by ion implantation. The ion implantation and epitaxial techniques developed for existing ion-implantation-and-epitaxial MOSFETs (IEMOSFETs) are herein utilized to protect the trench bottom and a relatively low-doped epitaxial channel layer with high mobility. By optimizing the geometry of p-base regions under a gate trench structure, we obtain a low specific on-resistance (R ON A) of 1.8 mΩ cm2 with a breakdown voltage (BVDSS) above 1200 V.

Demonstration of 13-kV class junction barrier Schottky diodes in 4H-SiC with three-zone junction termination extension

The static and dynamic characteristics of 13-kV class 4H-SiC junction barrier Schottky (JBS) diodes with a three-zone junction termination extension (JTE) are presented. Using an anisotropy breakdown model, technology computer-aided design simulation of devices with a three-zone JTE agrees well with the obtained experimental results, correctly predicting a sharp drop in blocking voltage at high JTE acceptor concentrations. The forward voltage of the JBS diode at 75°C and a forward current of 500 mA is reduced to approximately one-ninth by that of 13 series-connected 1000-V Si PiN diodes. This suggests that conduction losses of traditional high-voltage circuits which conventionally use series-connected devices can be drastically reduced by replacing the series-connected devices with a single 13-kV class SiC JBS diode. Moreover, the reverse recovery current waveform of the 13-kV class SiC JBS diode shows that these diodes have lower reverse recovery losses than a 13-kV SiC PiN diode.

1200 V SiC IE-UMOSFET with low on-resistance and high threshold voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

Carrier Lifetimes in 4H-SiC Epitaxial Layers on the C-Face Enhanced by Carbon Implantation

Carrier lifetime in low carrier concentration 4H-SiC epitaxial layers grown on the C-face was enhanced by using carbon implantation and post annealing. The measured carrier lifetime increased with the thickness of the epitaxial layer and was 11.4 µs for the 150 µm thick epitaxial layer. The internal carrier lifetime was estimated as 21 µs from the dependence of the measured carrier lifetime on the epitaxial layer thickness. This value is almost comparable to the reported values of the internal carrier lifetime for the layers grown on the Si-face.

Low on-resistance and fast switching of 13-kV SiC MOSFETs with optimized junction field-effect transistor region

In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with an optimized JFET region was fabricated with a 5 mm × 5 mm die size. The specific on-resistance (R<inf>onA</inf>) was estimated to be 169 mΩ·cm². The blocking voltage (BV<inf>DSS</inf>) of 13.1 kV was obtained at 10 μA/cm². Owing to a low electric field in the gate oxide (E<inf>ox</inf>), a threshold voltage (V<inf>th</inf>) shift within ± 0.06 V was achieved at the gate voltage of −15 V (equal to an electric field of −3 MV/cm) and 200 °C for 1000 hours. The dynamic test with inductive load resulted in turn-off and turn-on switching speeds of 75 kV/μs and 114 kV/μs, respectively, for the DC bus voltage of 10 kV at room temperature.

Systematic Investigation of 4H-SiC Trench Properties Dependence on Channel Concentration, Crystallographic Plane, and MOS Interface Treatment

We have systematically investigated the trench properties of 4H-SiC for p-type channel doping level formed by epitaxial growth, crystallographic plane, and MOS interface treatment. Our results show that the channel mobilities on the (1-100), (11-20), (-1100), and (-1-120) planes gradually decreased in the range from 1 × 1016 to 1 × 1017 cm-3 as the epitaxial channel concentration increased. An inevitable tradeoff existed between channel mobility (field-effect mobility, µFE) and threshold voltage (Vth) in trench MOSFETs. Furthermore, the maximum µFE at a channel concentration of 1 × 1017 cm-3 was 95 cm2·V-1·s-1 on the (11-20) plane with wet + hydrogen (H2) annealing, 83 cm2·V-1·s-1 on the (1-100) plane with wet + H2 annealing and 57 cm2·V-1·s-1 on the (1-100) plane with nitric oxide annealing.