Kazutoshi Kojima

Effect of gate oxidation method on electrical properties of metal-oxide-semiconductor field-effect transistors fabricated on 4H-SiC C(0001̄) face

The effect of gate oxidation method on the electrical properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on 4H-SiC C(0001) face has been investigated. In the case of SiC MOSFETs fabricated by dry gate oxidation, the peak value of field-effect mobility (μFE) is 16.3 cm2/V s. On the other hand, pyrogenic gate oxidation and pyrogenic gate oxidation followed by H2 postoxidation annealing (POA) considerably decreased the interface trap density (Dit) and the threshold voltage, and markedly improved the μFE. The depth profiles of hydrogen density were measured using secondary ion mass spectroscopy. These verified that pyrogenic gate oxidation increases hydrogen density at the SiO2/SiC interface compared to dry gate oxidation, and that the pyrogenic gate oxidation followed by H2 POA increases considerably it. It is thought that the Dit reduction might be caused by the passivation of interface states by –H or –OH. The peak value of μFE for SiC MOSFETs fabricated by pyrogenic gat...

Excellent effects of hydrogen postoxidation annealing on inversion channel mobility of 4H-SiC MOSFET fabricated on (11 2 0) face

Effects of hydrogen postoxidation annealing (H/sub 2/ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112~0) face have been investigated. As a result, an inversion channel mobility of 110 cm/sup 2//Vs was successfully achieved using H/sub 2/ POA at 800/spl deg/C for 30 min. H/sub 2/ POA reduces the interface trap density by about one order of magnitude compared with that without H/sub 2/ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H/sub 2/ POA. In addition, 4H-SiC MOSFET with H/sub 2/ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm/sup 2//Vs.

Impact ionization coefficients of 4H silicon carbide

Anisotropy of the impact ionization coefficients of 4H silicon carbide is investigated by means of the avalanche breakdown behavior of p+n diodes on (0001) and (112¯0) 4H silicon carbide epitaxial wafers. The impact ionization coefficients are extracted from the avalanche breakdown voltages and the multiplication of a reverse leakage current, due to impact ionization of these p+n diodes. The breakdown voltage of a p+n diode on a (112¯0) wafer is 60% of that on a (0001) wafer, and the extracted impact ionization coefficients of 4H silicon carbide show large anisotropy. We have shown that the anisotropy of the impact ionization coefficients is related to the anisotropy of carrier heating and drift velocity, which are due to the highly anisotropic electronic structure of 4H silicon carbide.

Correlation between reliability of thermal oxides and dislocations in n-type 4H-SiC epitaxial wafers

The correlation between thermal oxide reliability and dislocations in n-type 4H-SiC (0001) epitaxial wafers has been investigated. The thermal oxides were grown by dry oxidation at 1200°C followed by nitrogen postoxidation annealing. Charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations in a gate-oxide-forming area. Two types of dielectric breakdown modes, edge breakdown and dislocation-related breakdown, were confirmed by Nomarski microscopy. In addition, it is revealed that basal plane dislocation is the most common cause of the dislocation-related breakdown mode.

Measurement of Hall Mobility in 4H-SiC for Improvement of the Accuracy of the Mobility Model in Device Simulation

In order to construct a reliable parameter set for the physic al modeling of 4H-SiC, we are collecting and examining the physical parameters. The results of mobility measurement are presented and compared with the built-in model in the device simulator. The doping depe n nce of the electron mobility is in agreement with the built-in model, whereas that of the hole mobility is different from the built-in model in the higher doping region. Further, the anisotropy of the electron and hole mobility is investigated. The anisotropy of the electron mobility ) 0001 ( / ) 00 1 1 ( > < μ > < μ is about 0.83 and is in agreement with the built-in model. The anisotropy of the hole mobility is observed and it is estimated to be 1.15. To our knowledge, this is the first report of the anisotropy of the hole mobility in 4H-SiC. Introduction Silicon carbide devices have outstanding features, namely higher speed and lower loss than silicon devices. Among the many polytypes of SiC, 4H-SiC has attracted gre at att ntion as a candidate material for the next generation of power semiconductor devices, due t o the excellent physical properties such as the electric breakdown field and mobility. In order to r alize SiC devices that make the best use of the excellent physical properties, device simulati on technology of SiC is indispensable. However, the comprehensive and reliable parameter set for the physic al modeling of 4H-SiC for device simulators has not been reported. As a first step in the construction of a reliabl e par meter set for the physical modeling of 4H-SiC, we are collecting and examini ng the physical parameters systematically by fabricating test chips that consist of the el ments for physical property measurements. This paper is the first report on our ongoing research . The final goal of our research is the release of the comprehensive parameter set. In this paper, we present results of mobility measurement and compare them with the previous results. Experimental Figure 1 shows the top view of a test chip of the first lot. A prec ise patterning of contact, electrode and mesa by the mask process guarantees the precision of the physical property measurements. A test chip consists of elements (Hall bars and the square and clover shaped four terminal pattern) for mobility measurements and pin diodes for the impact ionization coefficient mea surements. Hall bars are tilted to the crystallographic axis every fifteenth degree in order to de ect the anisotropy of the mobility. Test chips were fabricated on 4H-SiC epitaxial wafers. For the measurements of the electron mobility, Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 443-446 doi:10.4028/www.scientific.net/MSF.433-436.443

The Electrical Characteristics of Metal-Oxide-Semiconductor Field Effect Transistors Fabricated on Cubic Silicon Carbide

The n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on cubic silicon carbide (3C-SiC) epitaxial layers grown on 3C-SiC substrates. The gate oxide of the MOSFETs was formed using pyrogenic oxidation at 1100 ?C. The 3C-SiC MOSFETs showed enhancement type behaviors after annealing at 200 ?C for 30 min in argon atmosphere. The maximum value of the effective channel mobility of the 3C-SiC MOSFETs was 260 cm2/V?s. The leakage current of gate oxide was of a few tens of nA/cm2 at an electric field range below 8.5 MV/cm, and breakdown began around 8.5 MV/cm.

N-channel MOSFETs fabricated on homoepitaxy-grown 3C-SiC films

We present results of the enhancement mode, n-channel 3C-silicon carbide (SiC) MOSFETs fabricated on homoepitaxy 3C-SiC films. The fabricated devices exhibit excellent gate-controlled linear and saturation regimes of operation. The average effective channel mobility is found to be 229 cm/sup 2//Vs. The breakdown field of the gate oxide is observed at be 11 MV/cm and the subthreshold swing is determined to be 280 mV/decade.

4H-SiC MOSFETs on C(000-,1) Face with Inversion Channel Mobility of 127cm2/Vs

SiC power MOSFETs is a promising candidate for the normally-off type fast switching device in the next generation. However, the on-resistance of SiC power MOSFETs is almost the same as that of Si IGBTs, which is much higher than the calculated value. This is caused by the low channel mobility due to high interface trap density. Large improvement of channel mobility is expected for SiC power MOSFETs with low on-resistance. We have already reported that the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(000 _ ,1) face was 72cm 2 /Vs, which is higher than the Si(0001) face. In this paper, we have investigated the effects of gate-oxidation temperature and H2 post oxidation annealing on the Dit of n-type MOS capacitors and the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(000 _ ,1) face. The Dit is reduced and the inversion channel mobility is improved as the gate-oxidation temperature decreases. The inversion channel mobility of 4H-SiC MOSFETs with the gate-oxide film grown at 900°C is 118cm 2 /Vs. Furthermore, using H2 POA, we have succeeded in the inversion channel mobility as high as 127cm 2 /Vs. This means that the C(000 _ ,1) face would be capable of SiC power MOSFETs with the high blocking voltage. Introduction SiC power MOSFETs is a promising candidate for the normally-off type fast switching device in the next generation. At present, the on-resistance of SiC power MOSFETs becomes the almost same as that of Si IGBT, which is much higher than the value predicted from the physical properties of SiC. This is caused by the low channel mobility due to high interface trap density (Dit). Recently, we have reported that the inversion channel mobility as high as 198cm 2 /Vs for 4H-SiC MOSFETs fabricated on the (11 _ ,20) face were achieved using the pyrogenic oxidation and the H2 post oxidation annealing (POA)[1]. However, the breakdown field of the (11 _ ,20) face in 4H-SiC is approximately 75% of the Si(0001) face[2]. The (11 _ ,20) face might be disadvantageous for the high power MOSFETs. In contrast, the C(000 _ ,1)face has the largest oxidation ratio, which is approximately 70% of that of Si[3]. This enables large reduction of oxidation process time in SiC MOSFETs fabrication. Furthermore, the C(000 _ ,1) face has the same breakdown field as the Si(0001)face[4]. The C(000 _ ,1) face is considered to be suitable for power SiC MOSFETs. We Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1417-1420 doi:10.4028/www.scientific.net/MSF.457-460.1417

Effects of Dislocations on Reliability of Thermal Oxides Grown on n-Type 4H-SiC Wafer

The effects of dislocations in n-type 4H-SiC(0001) epitaxial wafers on the reliability of thermal oxides have been investigated. Charge-to-breakdown (QBD) values of thermal oxides decrease with increase in the dislocations under a gate-oxide area. Nomarski microscope observations show that dielectric breakdown of thermal oxides occurs at the position of dislocation in epitaxial layer. It is reavealed that basal plane dislocation is the most common cause of the dielectric breakdown.

High Inversion Channel Mobility of MOSFET Fabricated on 4H-SiC C(000-1) Face Using H2 Post-Oxidation Annealing

We have investigated pyrogenic oxidation and H 2 POA effects on MOS capacitors and the inversion channel mobility of SiC MOSFET on the C(000 _ ,1) face. Even MOSFET with the gate oxide formed using only pyrogenic oxidation can operate. The fie ld-e f ct channel mobility( FE) is 52cm /Vs. The H2 post oxidation annealing reduces the interface state density, a nd improves the channel mobility. As a result, we succeeded in the high FE of 72cm /Vs for the MOSFET fabricated on the C(000 _ ,1) face. This suggests that the C(000 _ ,1) face is capable of SiC power MOSFETs with the high blocking voltage. Introduction SiC power MOSFET is expected for switching device in the next g neration. The on-resistance of SiC power MOSFET is much higher than the theoretical value be caus of the low channel mobility due to high interface state density (D it). Recently, we have reported that the channel mobilities as high as 50cm /Vs and 160cm/Vs for 4H-SiC MOSFET fabricated on the (0001) face and the (11 _ ,20) face were achieved by use of the pyrogenic re-oxidation anneali g and the H2 post oxidation annealing (POA), respectively[1],[2]. The value of 50cm /Vs is low for the theoretical on-resistance of SiC power MOSFETs. The breakdown field of the ( 11 _ ,20) face in 4H-SiC is 75% of the (0001) face[3]. There also are many stacking faults in epit axial layers on the bulk substrate grown using a seed of the (11 _ ,20) face, which lead to the large leakage current [4]. In contrast , he C(000 _ ,1) face has superior properties such as larger oxidation rate a nd smaller surface roughness as compared with the Si(0001) face[5],[6]. Furthermore, it has no sta cking faults. Therefore, the C(000 _ ,1) face is considered to be suitable for power SiC MOSFETs with high channel mobility and high blocking voltage. However, there is no report that the SiC M OSFET on the C(000 _ ,1) face operates without the channel doping, which attains only very low c hannel mobility in 6H-SiC MOSFET with positive threshold voltage(V th)[7]. We have reported that pyrogenic oxidation and H 2 POA reduced the D it near the conduction band edge in band gap[6]. This means that there is a Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 567-570 doi:10.4028/www.scientific.net/MSF.433-436.567