Hideo Ishida

A single-chip controller for 1.2 Gbps shared buffer ATM switches

A single chip controller for the shared buffer ATM switch with 1.2 Gbps switching capacity has been developed for the first time. Using external standard SRAMs enables low cost implementation of cell buffers, header translation tables and control memories. The chip can support various line interface speeds with standard UTOPIA level 2. High throughput multicast switching capability is achieved by novel buffer control scheme, re-queuing. The chip also supports multiple service classes standardized by the ATM forum. The performance of the developed chip is also evaluated.